Digital circuit design challenges and opportunities in the era of nanoscale CMOS

Benton H. Calhoun, Yu Cao, Xin Li, Ken Mai, Lawrence T. Pileggi, Rob A. Rutenbar, Kenneth L. Shepard

Research output: Contribution to journalArticle

121 Scopus citations

Abstract

Well-designed circuits are one key ldquoinsulatingrdquo layer between the increasingly unruly behavior of scaled complementary metal-oxide-semiconductor devices and the systems we seek to construct from them. As we move forward into the nanoscale regime, circuit design is burdened to ldquohiderdquo more of the problems intrinsic to deeply scaled devices. How this is being accomplished is the subject of this paper. We discuss new techniques for logic circuits and interconnect, for memory, and for clock and power distribution. We survey work to build accurate simulation models for nanoscale devices. We discuss the unique problems posed by nanoscale lithography and the role of geometrically regular circuits as one promising solution. Finally, we look at recent computer-aided design efforts in modeling, analysis, and optimization for nanoscale designs with ever increasing amounts of statistical variation.

Original languageEnglish (US)
Article number4403891
Pages (from-to)343-365
Number of pages23
JournalProceedings of the IEEE
Volume96
Issue number2
DOIs
StatePublished - Feb 2008

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Keywords

  • Clock distribution
  • Complementary metal-oxide-semiconductor (CMOS)
  • Device scaling
  • Digital circuits
  • Lithography
  • Logic
  • Manufacturability
  • Memory
  • Optimization
  • Power distribution
  • Regular circuit fabrics
  • Statistical variability
  • Yield

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Calhoun, B. H., Cao, Y., Li, X., Mai, K., Pileggi, L. T., Rutenbar, R. A., & Shepard, K. L. (2008). Digital circuit design challenges and opportunities in the era of nanoscale CMOS. Proceedings of the IEEE, 96(2), 343-365. [4403891]. https://doi.org/10.1109/JPROC.2007.911072