Abstract
This brief presents a digital background calibration technique that embraces comparator decision time to calibrate interstage gain errors and capacitor mismatches in pipelined analog-to-digital converters (ADCs). It does not modify the original analog signal path except for the addition of a comparator decision time binary quantizer built by simple digital gates. The technique does not limit either the ADC input signal swing or bandwidth. Simulation results for a 12-bit pipelined ADC show that the proposed technique can improve the signal- to-noise-and-distortion ratio (SNDR) and the spurious-free dynamic range (SFDR) from 44 and 48 dB to 72 and 86 dB, respectively. The SNDR convergence time is less than 3 × 106 cycles.
Original language | English (US) |
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Article number | 7001189 |
Pages (from-to) | 456-460 |
Number of pages | 5 |
Journal | IEEE Transactions on Circuits and Systems II: Express Briefs |
Volume | 62 |
Issue number | 5 |
DOIs | |
State | Published - May 1 2015 |
Externally published | Yes |
Keywords
- Comparator decision time
- digital background calibration
- pipelined analog-to-digital converters (ADCs)
ASJC Scopus subject areas
- Electrical and Electronic Engineering