Diastolic arrays: Throughput-driven reconfigurable computing

Myong Hyon Cho, Chih Chi Cheng, Michel Kinsy, G. Edward Suh, Srinivas Devadas

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Scopus citations

Abstract

Diastolic arrays are arrays of processing elements that communicate exclusively through First-In First-Out (FIFO) queues. FIFO visualization units enable relaxed timing of data transfers, and include hardware support to guarantee bandwidth and buffer space for all data transfers, which may follow composite paths through the network. We show that the architecture of diastolic arrays enables efficient synthesis from high-level specifications of communicating finite state machines so average throughput is maximized. Preliminary results are presented on an H.264 decoding benchmark.

Original languageEnglish (US)
Title of host publication2008 IEEE/ACM International Conference on Computer-Aided Design Digest of Technical Papers, ICCAD 2008
Pages457-464
Number of pages8
DOIs
StatePublished - 2008
Externally publishedYes
Event2008 International Conference on Computer-Aided Design, ICCAD - San Jose, CA, United States
Duration: Nov 10 2008Nov 13 2008

Publication series

NameIEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
ISSN (Print)1092-3152

Other

Other2008 International Conference on Computer-Aided Design, ICCAD
Country/TerritoryUnited States
CitySan Jose, CA
Period11/10/0811/13/08

ASJC Scopus subject areas

  • Software
  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design

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