The degradation of IC reliability is usually a gradual process. However, under some specific circumstance, the degradation rate can be dramatically accelerated, leading to a destructive result. Bias runaway, referring to the rapid increase of the bias voltage in analog/mixed signal (AMS) circuits, is such a case. It occurs when the feedback between the bias current and the effect of channel hot carrier (CHC) turns into positive and thus, uncontrollable. Such a catastrophic phenomenon is highly sensitive to the initial operation condition, as well as transistor gate length. Based on 65nm silicon data, this paper (1) investigates the critical condition that triggers bias runaway, and the impact of gate length tuning, (2) develops compact models and the simulation methodology for circuit diagnosis, and (3) proposes design solutions and the trade-offs to avoid bias runaway. Overall, this work identifies a key issue to the stability of bias generation circuits, which is vitally important to reliable AMS designs.