TY - GEN
T1 - Device and system level design considerations for analog-non-volatile-memory based neuromorphic architectures
AU - Eryilmaz, S. Burc
AU - Kuzum, Duygu
AU - Yu, Shimeng
AU - Wong, H. S Philip
N1 - Publisher Copyright:
© 2015 IEEE.
PY - 2015/2/16
Y1 - 2015/2/16
N2 - This paper gives an overview of recent progress in the brain-inspired computing field with a focus on implementation using emerging memories as electronic synapses. Design considerations and challenges such as requirements and design targets on multilevel states, device variability, programming energy, array-level connectivity, fan-in/fan-out, wire energy, and IR drop are presented. Wires are increasingly important in design decisions, especially for large systems; and cycle-to-cycle variations have large impact on learning performance.
AB - This paper gives an overview of recent progress in the brain-inspired computing field with a focus on implementation using emerging memories as electronic synapses. Design considerations and challenges such as requirements and design targets on multilevel states, device variability, programming energy, array-level connectivity, fan-in/fan-out, wire energy, and IR drop are presented. Wires are increasingly important in design decisions, especially for large systems; and cycle-to-cycle variations have large impact on learning performance.
UR - http://www.scopus.com/inward/record.url?scp=84964031980&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84964031980&partnerID=8YFLogxK
U2 - 10.1109/IEDM.2015.7409622
DO - 10.1109/IEDM.2015.7409622
M3 - Conference contribution
AN - SCOPUS:84964031980
T3 - Technical Digest - International Electron Devices Meeting, IEDM
SP - 4.1.1-4.1.4
BT - 2015 IEEE International Electron Devices Meeting, IEDM 2015
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 61st IEEE International Electron Devices Meeting, IEDM 2015
Y2 - 7 December 2015 through 9 December 2015
ER -