Development and empirical verification of an accuracy model for the power down leakage tests

Jae Woong Jeong, Sule Ozev, Friedrich Taenzler, Hui Chuan Chao

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Power down leakage (PDL) test is one of the most sensitive tests to verify device integrity during production test. Generally, the PDL current is measured once at the beginning and once at the end of the production test cycle in order to verify that the test process has not degraded device integrity. This current measurement is typically repeated 100 times or more to achieve accurate results. A wide variation in the measurement results usually necessitates additional measurements and averaging. However, without the proper modeling and analysis, repeating the measurement and averaging results alone will not guarantee the accuracy. In this paper, we analyze root causes of the error for the PDL current measurements. Our analysis indicates that while quantization error and thermal noise have negligible impact on the error of the measurements, the instrument accuracy, timing, and temperature based variation are the major contributors to accuracy. We develop a new accuracy model for the PDL current measurement to account for these major contributors. Using this model, we propose a new systematic optimization method for the test process to achieve the desired accuracy without increasing the test time unreasonably. This method and the model are empirically verified with hardware experiments. With hardware experiments we also show that we can reduce the test time nearly 3-fold using the optimized test sequencing strategy.

Original languageEnglish (US)
Title of host publicationProceedings - 2014 IEEE 32nd VLSI Test Symposium, VTS 2014
PublisherIEEE Computer Society
ISBN (Print)9781479926114
DOIs
StatePublished - Jan 1 2014
Event2014 IEEE 32nd VLSI Test Symposium, VTS 2014 - Napa, CA, United States
Duration: Apr 13 2014Apr 17 2014

Publication series

NameProceedings of the IEEE VLSI Test Symposium

Other

Other2014 IEEE 32nd VLSI Test Symposium, VTS 2014
CountryUnited States
CityNapa, CA
Period4/13/144/17/14

ASJC Scopus subject areas

  • Computer Science Applications
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Development and empirical verification of an accuracy model for the power down leakage tests'. Together they form a unique fingerprint.

  • Cite this

    Jeong, J. W., Ozev, S., Taenzler, F., & Chao, H. C. (2014). Development and empirical verification of an accuracy model for the power down leakage tests. In Proceedings - 2014 IEEE 32nd VLSI Test Symposium, VTS 2014 [6818786] (Proceedings of the IEEE VLSI Test Symposium). IEEE Computer Society. https://doi.org/10.1109/VTS.2014.6818786