Determination of optimum on-chip bypass capacitor in CMOS VLSI systems to reduce switching noise

Balaji Kanigicherla; Sung Hun Oh; David Allee

Determination of optimum on-chip bypass capacitor in CMOS VLSI systems to reduce switching noise

Balaji Kanigicherla, Sung Hun Oh, David Allee

Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

An analytical model for switching noise with an on-chip bypass capacitor is presented. To incorporate various design parameters into the model, a differential equation is formulated and solved by Laplace transforms. Based on the model, optimum on-chip capacitor size is determined and compared with HSPICE simulation results. In the simulation, a realistic 0.6 μm BSIM device model at best process conditions is used and good correlation is demonstrated.

Original language	English (US)
Title of host publication	Proceedings - IEEE International Symposium on Circuits and Systems
Editors	Anon
Publisher	IEEE
Pages	1724-1727
Number of pages	4
Volume	3
State	Published - 1997
Event	Proceedings of the 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97. Part 4 (of 4) - Hong Kong, Hong Kong Duration: Jun 9 1997 → Jun 12 1997

Other

Other	Proceedings of the 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97. Part 4 (of 4)
City	Hong Kong, Hong Kong
Period	6/9/97 → 6/12/97

ASJC Scopus subject areas

Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

Cite this

Kanigicherla, B, Oh, SH & Allee, D 1997, Determination of optimum on-chip bypass capacitor in CMOS VLSI systems to reduce switching noise. in Anon (ed.), Proceedings - IEEE International Symposium on Circuits and Systems. vol. 3, IEEE, pp. 1724-1727, Proceedings of the 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97. Part 4 (of 4), Hong Kong, Hong Kong, 6/9/97.

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title = "Determination of optimum on-chip bypass capacitor in CMOS VLSI systems to reduce switching noise",

abstract = "An analytical model for switching noise with an on-chip bypass capacitor is presented. To incorporate various design parameters into the model, a differential equation is formulated and solved by Laplace transforms. Based on the model, optimum on-chip capacitor size is determined and compared with HSPICE simulation results. In the simulation, a realistic 0.6 μm BSIM device model at best process conditions is used and good correlation is demonstrated.",

author = "Balaji Kanigicherla and Oh, {Sung Hun} and David Allee",

year = "1997",

language = "English (US)",

volume = "3",

pages = "1724--1727",

editor = "Anon",

booktitle = "Proceedings - IEEE International Symposium on Circuits and Systems",

publisher = "IEEE",

note = "Proceedings of the 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97. Part 4 (of 4) ; Conference date: 09-06-1997 Through 12-06-1997",

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AU - Kanigicherla, Balaji

AU - Oh, Sung Hun

AU - Allee, David

PY - 1997

Y1 - 1997

N2 - An analytical model for switching noise with an on-chip bypass capacitor is presented. To incorporate various design parameters into the model, a differential equation is formulated and solved by Laplace transforms. Based on the model, optimum on-chip capacitor size is determined and compared with HSPICE simulation results. In the simulation, a realistic 0.6 μm BSIM device model at best process conditions is used and good correlation is demonstrated.

AB - An analytical model for switching noise with an on-chip bypass capacitor is presented. To incorporate various design parameters into the model, a differential equation is formulated and solved by Laplace transforms. Based on the model, optimum on-chip capacitor size is determined and compared with HSPICE simulation results. In the simulation, a realistic 0.6 μm BSIM device model at best process conditions is used and good correlation is demonstrated.

UR - http://www.scopus.com/inward/record.url?scp=0030673753&partnerID=8YFLogxK

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M3 - Conference contribution

AN - SCOPUS:0030673753

VL - 3

SP - 1724

EP - 1727

BT - Proceedings - IEEE International Symposium on Circuits and Systems

A2 - Anon, null

PB - IEEE

T2 - Proceedings of the 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97. Part 4 (of 4)

Y2 - 9 June 1997 through 12 June 1997

ER -

Determination of optimum on-chip bypass capacitor in CMOS VLSI systems to reduce switching noise

Abstract

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ASJC Scopus subject areas

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