Determination of optimum on-chip bypass capacitor in CMOS VLSI systems to reduce switching noise

Balaji Kanigicherla, Sung Hun Oh, David Allee

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

An analytical model for switching noise with an on-chip bypass capacitor is presented. To incorporate various design parameters into the model, a differential equation is formulated and solved by Laplace transforms. Based on the model, optimum on-chip capacitor size is determined and compared with HSPICE simulation results. In the simulation, a realistic 0.6 μm BSIM device model at best process conditions is used and good correlation is demonstrated.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
Editors Anon
PublisherIEEE
Pages1724-1727
Number of pages4
Volume3
StatePublished - 1997
EventProceedings of the 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97. Part 4 (of 4) - Hong Kong, Hong Kong
Duration: Jun 9 1997Jun 12 1997

Other

OtherProceedings of the 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97. Part 4 (of 4)
CityHong Kong, Hong Kong
Period6/9/976/12/97

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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