Determination of optimum on-chip bypass capacitor in CMOS VLSI systems to reduce switching noise

Balaji Kanigicherla, Sung Hun Oh, David Allee

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

An analytical model for switching noise with an on-chip bypass capacitor is presented. To incorporate various design parameters into the model, a differential equation is formulated and solved by Laplace transforms. Based on the model, optimum on-chip capacitor size is determined and compared with HSPICE simulation results. In the simulation, a realistic 0.6 μm BSIM device model at best process conditions is used and good correlation is demonstrated.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
Editors Anon
PublisherIEEE
Pages1724-1727
Number of pages4
Volume3
StatePublished - 1997
EventProceedings of the 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97. Part 4 (of 4) - Hong Kong, Hong Kong
Duration: Jun 9 1997Jun 12 1997

Other

OtherProceedings of the 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97. Part 4 (of 4)
CityHong Kong, Hong Kong
Period6/9/976/12/97

Fingerprint

Capacitors
Laplace transforms
Analytical models
Differential equations

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Kanigicherla, B., Oh, S. H., & Allee, D. (1997). Determination of optimum on-chip bypass capacitor in CMOS VLSI systems to reduce switching noise. In Anon (Ed.), Proceedings - IEEE International Symposium on Circuits and Systems (Vol. 3, pp. 1724-1727). IEEE.

Determination of optimum on-chip bypass capacitor in CMOS VLSI systems to reduce switching noise. / Kanigicherla, Balaji; Oh, Sung Hun; Allee, David.

Proceedings - IEEE International Symposium on Circuits and Systems. ed. / Anon. Vol. 3 IEEE, 1997. p. 1724-1727.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kanigicherla, B, Oh, SH & Allee, D 1997, Determination of optimum on-chip bypass capacitor in CMOS VLSI systems to reduce switching noise. in Anon (ed.), Proceedings - IEEE International Symposium on Circuits and Systems. vol. 3, IEEE, pp. 1724-1727, Proceedings of the 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97. Part 4 (of 4), Hong Kong, Hong Kong, 6/9/97.
Kanigicherla B, Oh SH, Allee D. Determination of optimum on-chip bypass capacitor in CMOS VLSI systems to reduce switching noise. In Anon, editor, Proceedings - IEEE International Symposium on Circuits and Systems. Vol. 3. IEEE. 1997. p. 1724-1727
Kanigicherla, Balaji ; Oh, Sung Hun ; Allee, David. / Determination of optimum on-chip bypass capacitor in CMOS VLSI systems to reduce switching noise. Proceedings - IEEE International Symposium on Circuits and Systems. editor / Anon. Vol. 3 IEEE, 1997. pp. 1724-1727
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