Design with sub-10 nm FinFET technologies

Lawrence T. Clark; Vinay Vashishtha

doi:10.1109/CICC.2017.7993720

Design with sub-10 nm FinFET technologies

Lawrence T. Clark, Vinay Vashishtha

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Scopus citations

Abstract

• The close interaction of the process capabilities requires that the circuit and physical design architecture be comprehended - This is classical 'Design Technology Co-optimization' (DTCO) • Only increasing over time • Memory transistor design must anticipate the required - Read and write assists • And their impact on area • Denser cell libraries restrict the possible cells - Smaller libraries are an inevitable result • Complex cells with breaks are better assembled by the APR tool • Flexible sizing and placement with multiple cells • At all points in the design process the anticipated physical design has to be understood - The lines/cuts metallization is an example of these requirements • APR tools must calculate the parasitics of moving cuts and the extra dummy metals as the design is routed to avoid large critical path impact.

Original language	English (US)
Title of host publication	38th Annual Custom Integrated Circuits Conference
Subtitle of host publication	A Showcase for Integrated Circuit Design in Silicon Hills, CICC 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781509051915
DOIs	https://doi.org/10.1109/CICC.2017.7993720
State	Published - Jul 26 2017
Event	38th Annual Custom Integrated Circuits Conference, CICC 2017 - Austin, United States Duration: Apr 30 2017 → May 3 2017

Publication series

Name	Proceedings of the Custom Integrated Circuits Conference
Volume	2017-April
ISSN (Print)	0886-5930

Other

Other	38th Annual Custom Integrated Circuits Conference, CICC 2017
Country	United States
City	Austin
Period	4/30/17 → 5/3/17

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/CICC.2017.7993720

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Cite this

Clark, L. T., & Vashishtha, V. (2017). Design with sub-10 nm FinFET technologies. In 38th Annual Custom Integrated Circuits Conference: A Showcase for Integrated Circuit Design in Silicon Hills, CICC 2017 [7993720] (Proceedings of the Custom Integrated Circuits Conference; Vol. 2017-April). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CICC.2017.7993720

Design with sub-10 nm FinFET technologies. / Clark, Lawrence T.; Vashishtha, Vinay.

38th Annual Custom Integrated Circuits Conference: A Showcase for Integrated Circuit Design in Silicon Hills, CICC 2017. Institute of Electrical and Electronics Engineers Inc., 2017. 7993720 (Proceedings of the Custom Integrated Circuits Conference; Vol. 2017-April).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Clark, LT & Vashishtha, V 2017, Design with sub-10 nm FinFET technologies. in 38th Annual Custom Integrated Circuits Conference: A Showcase for Integrated Circuit Design in Silicon Hills, CICC 2017., 7993720, Proceedings of the Custom Integrated Circuits Conference, vol. 2017-April, Institute of Electrical and Electronics Engineers Inc., 38th Annual Custom Integrated Circuits Conference, CICC 2017, Austin, United States, 4/30/17. https://doi.org/10.1109/CICC.2017.7993720

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