Abstract
• The close interaction of the process capabilities requires that the circuit and physical design architecture be comprehended - This is classical 'Design Technology Co-optimization' (DTCO) • Only increasing over time • Memory transistor design must anticipate the required - Read and write assists • And their impact on area • Denser cell libraries restrict the possible cells - Smaller libraries are an inevitable result • Complex cells with breaks are better assembled by the APR tool • Flexible sizing and placement with multiple cells • At all points in the design process the anticipated physical design has to be understood - The lines/cuts metallization is an example of these requirements • APR tools must calculate the parasitics of moving cuts and the extra dummy metals as the design is routed to avoid large critical path impact.
| Original language | English (US) |
|---|---|
| Title of host publication | 38th Annual Custom Integrated Circuits Conference |
| Subtitle of host publication | A Showcase for Integrated Circuit Design in Silicon Hills, CICC 2017 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Volume | 2017-April |
| ISBN (Electronic) | 9781509051915 |
| DOIs | |
| State | Published - Jul 26 2017 |
| Event | 38th Annual Custom Integrated Circuits Conference, CICC 2017 - Austin, United States Duration: Apr 30 2017 → May 3 2017 |
Other
| Other | 38th Annual Custom Integrated Circuits Conference, CICC 2017 |
|---|---|
| Country | United States |
| City | Austin |
| Period | 4/30/17 → 5/3/17 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering