Design with sub-10 nm FinFET technologies

Lawrence T. Clark, Vinay Vashishtha

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

• The close interaction of the process capabilities requires that the circuit and physical design architecture be comprehended - This is classical 'Design Technology Co-optimization' (DTCO) • Only increasing over time • Memory transistor design must anticipate the required - Read and write assists • And their impact on area • Denser cell libraries restrict the possible cells - Smaller libraries are an inevitable result • Complex cells with breaks are better assembled by the APR tool • Flexible sizing and placement with multiple cells • At all points in the design process the anticipated physical design has to be understood - The lines/cuts metallization is an example of these requirements • APR tools must calculate the parasitics of moving cuts and the extra dummy metals as the design is routed to avoid large critical path impact.

Original languageEnglish (US)
Title of host publication38th Annual Custom Integrated Circuits Conference
Subtitle of host publicationA Showcase for Integrated Circuit Design in Silicon Hills, CICC 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Volume2017-April
ISBN (Electronic)9781509051915
DOIs
StatePublished - Jul 26 2017
Event38th Annual Custom Integrated Circuits Conference, CICC 2017 - Austin, United States
Duration: Apr 30 2017May 3 2017

Other

Other38th Annual Custom Integrated Circuits Conference, CICC 2017
CountryUnited States
CityAustin
Period4/30/175/3/17

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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    Clark, L. T., & Vashishtha, V. (2017). Design with sub-10 nm FinFET technologies. In 38th Annual Custom Integrated Circuits Conference: A Showcase for Integrated Circuit Design in Silicon Hills, CICC 2017 (Vol. 2017-April). [7993720] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CICC.2017.7993720