TY - GEN
T1 - Design with sub-10 nm FinFET technologies
AU - Clark, Lawrence T.
AU - Vashishtha, Vinay
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2017/7/26
Y1 - 2017/7/26
N2 - • The close interaction of the process capabilities requires that the circuit and physical design architecture be comprehended - This is classical 'Design Technology Co-optimization' (DTCO) • Only increasing over time • Memory transistor design must anticipate the required - Read and write assists • And their impact on area • Denser cell libraries restrict the possible cells - Smaller libraries are an inevitable result • Complex cells with breaks are better assembled by the APR tool • Flexible sizing and placement with multiple cells • At all points in the design process the anticipated physical design has to be understood - The lines/cuts metallization is an example of these requirements • APR tools must calculate the parasitics of moving cuts and the extra dummy metals as the design is routed to avoid large critical path impact.
AB - • The close interaction of the process capabilities requires that the circuit and physical design architecture be comprehended - This is classical 'Design Technology Co-optimization' (DTCO) • Only increasing over time • Memory transistor design must anticipate the required - Read and write assists • And their impact on area • Denser cell libraries restrict the possible cells - Smaller libraries are an inevitable result • Complex cells with breaks are better assembled by the APR tool • Flexible sizing and placement with multiple cells • At all points in the design process the anticipated physical design has to be understood - The lines/cuts metallization is an example of these requirements • APR tools must calculate the parasitics of moving cuts and the extra dummy metals as the design is routed to avoid large critical path impact.
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U2 - 10.1109/CICC.2017.7993720
DO - 10.1109/CICC.2017.7993720
M3 - Conference contribution
AN - SCOPUS:85030475926
T3 - Proceedings of the Custom Integrated Circuits Conference
BT - 38th Annual Custom Integrated Circuits Conference
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 38th Annual Custom Integrated Circuits Conference, CICC 2017
Y2 - 30 April 2017 through 3 May 2017
ER -