The 3-D integration of resistive switching random access memory (RRAM) array is attractive for low-cost and high-density nonvolatile memory application. In this paper, the design tradeoffs of select transistor drivability, RRAM device characteristics, such as switching current (IW), ON/OFF-state resistance (RON/ROFF), and I-V nonlinearity ratio, interconnect material, and write/read scheme are systematically analyzed using a 3-D circuit simulation. The simulation results show that insufficient current drivability of the vertical transistor severely limits the number of 3-D layers. A low switching current (high RON) or a high nonlinearity is beneficial for improving the write margin, while it degrades the read current sense margin. To alleviate this conflict, the read voltage needs to be boosted to the half write voltage. The common RRAM electrode material TiN is not suitable for the interconnect material due to a high resistivity. To improve write energy efficiency, a multiple-bit write scheme is proposed to reduce the write energy consumption per bit and enable a high bandwidth. With RON = 500 kΩ (IW = 6 μA) and nonlinearity ratio = 10, 1-Mb 3-D vertical RRAM subarray is feasible to meet the specified write/read margin with ~2-pJ/bit energy consumption.
|Original language||English (US)|
|Journal||IEEE Transactions on Very Large Scale Integration (VLSI) Systems|
|State||Accepted/In press - Apr 27 2016|
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Hardware and Architecture