Abstract

The 3-D integration of resistive switching random access memory (RRAM) array is attractive for low-cost and high-density nonvolatile memory application. In this paper, the design tradeoffs of select transistor drivability, RRAM device characteristics, such as switching current (IW), on/off-state resistance (RON/ROFF), and I-V nonlinearity ratio, interconnect material, and write/read scheme are systematically analyzed using a 3-D circuit simulation. The simulation results show that insufficient current drivability of the vertical transistor severely limits the number of 3-D layers. A low switching current (high RON) or a high nonlinearity is beneficial for improving the write margin, while it degrades the read current sense margin. To alleviate this conflict, the read voltage needs to be boosted to the half write voltage. The common RRAM electrode material TiN is not suitable for the interconnect material due to a high resistivity. To improve write energy efficiency, a multiple-bit write scheme is proposed to reduce the write energy consumption per bit and enable a high bandwidth. With RON =500 k Ω (IW=6 μA) and nonlinearity ratio =10 , 1-Mb 3-D vertical RRAM subarray is feasible to meet the specified write/read margin with ∼ 2-pJ/bit energy consumption.

Original languageEnglish (US)
Article number7460981
Pages (from-to)3460-3467
Number of pages8
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume24
Issue number12
DOIs
StatePublished - Dec 2016

Keywords

  • 3-D integration
  • ReRAM
  • Resistive switching random access memory (RRAM)
  • cross-point array
  • resistive random access memory

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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