Design technology co-optimization of back end of line design rules for a 7 nm predictive process design kit

Vinay Vashishtha, Ankita Dosi, Lovish Masand, Lawrence T. Clark

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

This paper discusses the back-end-of-line (BEOL) layers for a 7 nm predictive process design kit (PDK). The rationale behind choosing a particular lithographic process - EUV lithography, self-aligned double patterning (SADP), and litho-etch litho-etch (LELE) - for different layers, in addition to some design rule values, is described. The rules are based on the literature and on design technology co-optimization (DTCO) evaluation of standard cell based designs and automated place-and-route experiments. Decomposition criteria and design rules to ensure conflict-free coloring of SADP metal topologies and manufacturable SADP photolithography masks are discussed in detail. Their efficacy is demonstrated through successful coloring and photolithography mask derivation for target metal shape layouts, which represent corner cases, by using the Mentor Graphics Calibre and multi-patterning tools. Edge placement errors, misalignment, and critical dimension uniformity are included in the analysis.

Original languageEnglish (US)
Title of host publicationProceedings of the 18th International Symposium on Quality Electronic Design, ISQED 2017
PublisherIEEE Computer Society
Pages149-154
Number of pages6
ISBN (Electronic)9781509054046
DOIs
StatePublished - May 2 2017
Event18th International Symposium on Quality Electronic Design, ISQED 2017 - Santa Clara, United States
Duration: Mar 14 2017Mar 15 2017

Other

Other18th International Symposium on Quality Electronic Design, ISQED 2017
CountryUnited States
CitySanta Clara
Period3/14/173/15/17

Fingerprint

Process design
Photolithography
Coloring
Masks
Extreme ultraviolet lithography
Metals
Topology
Decomposition
Experiments

Keywords

  • Back end of line
  • design rules
  • EUV lithography
  • LELE
  • multi-patterning
  • SADP

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

Cite this

Vashishtha, V., Dosi, A., Masand, L., & Clark, L. T. (2017). Design technology co-optimization of back end of line design rules for a 7 nm predictive process design kit. In Proceedings of the 18th International Symposium on Quality Electronic Design, ISQED 2017 (pp. 149-154). [7918308] IEEE Computer Society. https://doi.org/10.1109/ISQED.2017.7918308

Design technology co-optimization of back end of line design rules for a 7 nm predictive process design kit. / Vashishtha, Vinay; Dosi, Ankita; Masand, Lovish; Clark, Lawrence T.

Proceedings of the 18th International Symposium on Quality Electronic Design, ISQED 2017. IEEE Computer Society, 2017. p. 149-154 7918308.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Vashishtha, V, Dosi, A, Masand, L & Clark, LT 2017, Design technology co-optimization of back end of line design rules for a 7 nm predictive process design kit. in Proceedings of the 18th International Symposium on Quality Electronic Design, ISQED 2017., 7918308, IEEE Computer Society, pp. 149-154, 18th International Symposium on Quality Electronic Design, ISQED 2017, Santa Clara, United States, 3/14/17. https://doi.org/10.1109/ISQED.2017.7918308
Vashishtha V, Dosi A, Masand L, Clark LT. Design technology co-optimization of back end of line design rules for a 7 nm predictive process design kit. In Proceedings of the 18th International Symposium on Quality Electronic Design, ISQED 2017. IEEE Computer Society. 2017. p. 149-154. 7918308 https://doi.org/10.1109/ISQED.2017.7918308
Vashishtha, Vinay ; Dosi, Ankita ; Masand, Lovish ; Clark, Lawrence T. / Design technology co-optimization of back end of line design rules for a 7 nm predictive process design kit. Proceedings of the 18th International Symposium on Quality Electronic Design, ISQED 2017. IEEE Computer Society, 2017. pp. 149-154
@inproceedings{3e7af22f203e4fb28603c34a86086155,
title = "Design technology co-optimization of back end of line design rules for a 7 nm predictive process design kit",
abstract = "This paper discusses the back-end-of-line (BEOL) layers for a 7 nm predictive process design kit (PDK). The rationale behind choosing a particular lithographic process - EUV lithography, self-aligned double patterning (SADP), and litho-etch litho-etch (LELE) - for different layers, in addition to some design rule values, is described. The rules are based on the literature and on design technology co-optimization (DTCO) evaluation of standard cell based designs and automated place-and-route experiments. Decomposition criteria and design rules to ensure conflict-free coloring of SADP metal topologies and manufacturable SADP photolithography masks are discussed in detail. Their efficacy is demonstrated through successful coloring and photolithography mask derivation for target metal shape layouts, which represent corner cases, by using the Mentor Graphics Calibre and multi-patterning tools. Edge placement errors, misalignment, and critical dimension uniformity are included in the analysis.",
keywords = "Back end of line, design rules, EUV lithography, LELE, multi-patterning, SADP",
author = "Vinay Vashishtha and Ankita Dosi and Lovish Masand and Clark, {Lawrence T.}",
year = "2017",
month = "5",
day = "2",
doi = "10.1109/ISQED.2017.7918308",
language = "English (US)",
pages = "149--154",
booktitle = "Proceedings of the 18th International Symposium on Quality Electronic Design, ISQED 2017",
publisher = "IEEE Computer Society",
address = "United States",

}

TY - GEN

T1 - Design technology co-optimization of back end of line design rules for a 7 nm predictive process design kit

AU - Vashishtha, Vinay

AU - Dosi, Ankita

AU - Masand, Lovish

AU - Clark, Lawrence T.

PY - 2017/5/2

Y1 - 2017/5/2

N2 - This paper discusses the back-end-of-line (BEOL) layers for a 7 nm predictive process design kit (PDK). The rationale behind choosing a particular lithographic process - EUV lithography, self-aligned double patterning (SADP), and litho-etch litho-etch (LELE) - for different layers, in addition to some design rule values, is described. The rules are based on the literature and on design technology co-optimization (DTCO) evaluation of standard cell based designs and automated place-and-route experiments. Decomposition criteria and design rules to ensure conflict-free coloring of SADP metal topologies and manufacturable SADP photolithography masks are discussed in detail. Their efficacy is demonstrated through successful coloring and photolithography mask derivation for target metal shape layouts, which represent corner cases, by using the Mentor Graphics Calibre and multi-patterning tools. Edge placement errors, misalignment, and critical dimension uniformity are included in the analysis.

AB - This paper discusses the back-end-of-line (BEOL) layers for a 7 nm predictive process design kit (PDK). The rationale behind choosing a particular lithographic process - EUV lithography, self-aligned double patterning (SADP), and litho-etch litho-etch (LELE) - for different layers, in addition to some design rule values, is described. The rules are based on the literature and on design technology co-optimization (DTCO) evaluation of standard cell based designs and automated place-and-route experiments. Decomposition criteria and design rules to ensure conflict-free coloring of SADP metal topologies and manufacturable SADP photolithography masks are discussed in detail. Their efficacy is demonstrated through successful coloring and photolithography mask derivation for target metal shape layouts, which represent corner cases, by using the Mentor Graphics Calibre and multi-patterning tools. Edge placement errors, misalignment, and critical dimension uniformity are included in the analysis.

KW - Back end of line

KW - design rules

KW - EUV lithography

KW - LELE

KW - multi-patterning

KW - SADP

UR - http://www.scopus.com/inward/record.url?scp=85019595683&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85019595683&partnerID=8YFLogxK

U2 - 10.1109/ISQED.2017.7918308

DO - 10.1109/ISQED.2017.7918308

M3 - Conference contribution

SP - 149

EP - 154

BT - Proceedings of the 18th International Symposium on Quality Electronic Design, ISQED 2017

PB - IEEE Computer Society

ER -