Design space exploration of ovonic threshold switch (OTS) for sub-threshold read operation in cross-point memory arrays

Jiyong Woo, Shimeng Yu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We perform SPICE based simulations to identify the possibility and challenges of a sub-threshold read operation in a cross-point one-selector and one-resistive memory (1S-1R) array enabled by an ovonic threshold switch (OTS) with a high threshold voltage (Vth) and strong non-linearity of a sub-threshold regime. Here, it is important to read an on/off ratio below the Vth, where the OTS has not yet been turned on, leading to robust reliability characteristics of the 1S-1R. We show that the on/off ratio can be observed by adjusting the resistance range of the memory close to the threshold resistance of the OTS. Then, increasing the non-linearity in the sub-threshold regime of the OTS improves the on/off ratio. However, reading the obtained on/off ratio even in very small array is difficult due to sneak-path currents. Therefore, a low off-current of the OTS should be lower than 0.1 nA at 1 V to ensure a minimum readable on/off ratio (~2 ×) in the array.

Original languageEnglish (US)
Title of host publication2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728103976
DOIs
StatePublished - Jan 1 2019
Event2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Sapporo, Japan
Duration: May 26 2019May 29 2019

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
Volume2019-May
ISSN (Print)0271-4310

Conference

Conference2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019
CountryJapan
CitySapporo
Period5/26/195/29/19

Fingerprint

Switches
Data storage equipment
SPICE
Threshold voltage

Keywords

  • Cross-point array
  • Read disturbance
  • Resistive memory
  • Selector
  • Sub-threshold read scheme

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Woo, J., & Yu, S. (2019). Design space exploration of ovonic threshold switch (OTS) for sub-threshold read operation in cross-point memory arrays. In 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings [8702296] (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2019-May). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2019.8702296

Design space exploration of ovonic threshold switch (OTS) for sub-threshold read operation in cross-point memory arrays. / Woo, Jiyong; Yu, Shimeng.

2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2019. 8702296 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2019-May).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Woo, J & Yu, S 2019, Design space exploration of ovonic threshold switch (OTS) for sub-threshold read operation in cross-point memory arrays. in 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings., 8702296, Proceedings - IEEE International Symposium on Circuits and Systems, vol. 2019-May, Institute of Electrical and Electronics Engineers Inc., 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019, Sapporo, Japan, 5/26/19. https://doi.org/10.1109/ISCAS.2019.8702296
Woo J, Yu S. Design space exploration of ovonic threshold switch (OTS) for sub-threshold read operation in cross-point memory arrays. In 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2019. 8702296. (Proceedings - IEEE International Symposium on Circuits and Systems). https://doi.org/10.1109/ISCAS.2019.8702296
Woo, Jiyong ; Yu, Shimeng. / Design space exploration of ovonic threshold switch (OTS) for sub-threshold read operation in cross-point memory arrays. 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2019. (Proceedings - IEEE International Symposium on Circuits and Systems).
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