Design sensitivity of single event transients in scaled logic circuits

Jyothi Velamala, Robert LiVolsi, Myra Torres, Yu Cao

Research output: Chapter in Book/Report/Conference proceedingConference contribution

13 Scopus citations

Abstract

Single Event Transients (SET) in digital logic pose an ever increasing reliability challenge as device dimensions shrink in modern technologies. Projection of SET sensitivity with scaling is essential to assess the logic failure and error probability in modern technology generations. This paper discusses the effects of device scaling from 45nm to 12nm processes and circuit parameter tuning on SETs. The failure due to particle strikes i.e., Single Event upsets (SEU) as well as its behavior with process variations and reliability mechanisms such as NBTI is evaluated in this work. The critical supply voltage required to avoid SET propagation with circuit parameters is investigated. This work also proposes a probability model which examines the propagation of SET at any node to the output of a circuit. The proposed methodology can be extended to any complex digital circuit to investigate its vulnerability to SET.

Original languageEnglish (US)
Title of host publication2011 48th ACM/EDAC/IEEE Design Automation Conference, DAC 2011
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages694-699
Number of pages6
ISBN (Print)9781450306362
DOIs
StatePublished - Jan 1 2011

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0738-100X

Keywords

  • Critical Voltage
  • Double Exponential Current Pulse
  • Failure Probability
  • Single Event Transients

ASJC Scopus subject areas

  • Control and Systems Engineering
  • Computer Science Applications
  • Electrical and Electronic Engineering
  • Modeling and Simulation

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