Design sensitivities to variability: Extrapolations and assessments in nanometer VLSI

Y. Cao; P. Gupta; A. B. Kahng; D. Sylvester; J. Yang

doi:10.1109/ASIC.2002.1158094

Design sensitivities to variability: Extrapolations and assessments in nanometer VLSI

Y. Cao, P. Gupta, A. B. Kahng, D. Sylvester, J. Yang

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

74 Scopus citations

Abstract

We propose a new framework for assessing (1) the impact of process variation on circuit performance and product value, and (2) the respective returns on investment for alternative process improvements. Elements of our framework include accurate device models and circuit simulation, along with Monte-Carlo analyses, to estimate parametric yields. We evaluate the merits of taking into account such previously unconsidered phenomena as correlations among process parameters. We also evaluate the impact of process variation with respect to such relevant metrics as parametric yield at selling point, and amount of required design guardbanding. Our experimental results yield insights into the scaling of process variation impacts through the next two ITRS technology nodes.

Original language	English (US)
Title of host publication	Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002
Editors	John Chickanosky, Ram K. Krishnamurthy, P.R. Mukund
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	411-415
Number of pages	5
ISBN (Electronic)	0780374940
DOIs	https://doi.org/10.1109/ASIC.2002.1158094
State	Published - 2002
Externally published	Yes
Event	15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002 - Rochester, United States Duration: Sep 25 2002 → Sep 28 2002

Publication series

Name	Proceedings of the Annual IEEE International ASIC Conference and Exhibit
Volume	2002-January
ISSN (Print)	1063-0988

Other

Other	15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002
Country/Territory	United States
City	Rochester
Period	9/25/02 → 9/28/02

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/ASIC.2002.1158094

Cite this

Cao, Y., Gupta, P., Kahng, A. B., Sylvester, D., & Yang, J. (2002). Design sensitivities to variability: Extrapolations and assessments in nanometer VLSI. In J. Chickanosky, R. K. Krishnamurthy, & P. R. Mukund (Eds.), Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002 (pp. 411-415). [1158094] (Proceedings of the Annual IEEE International ASIC Conference and Exhibit; Vol. 2002-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASIC.2002.1158094

Design sensitivities to variability : Extrapolations and assessments in nanometer VLSI. / Cao, Y.; Gupta, P.; Kahng, A. B. et al.

Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002. ed. / John Chickanosky; Ram K. Krishnamurthy; P.R. Mukund. Institute of Electrical and Electronics Engineers Inc., 2002. p. 411-415 1158094 (Proceedings of the Annual IEEE International ASIC Conference and Exhibit; Vol. 2002-January).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Cao, Y, Gupta, P, Kahng, AB, Sylvester, D & Yang, J 2002, Design sensitivities to variability: Extrapolations and assessments in nanometer VLSI. in J Chickanosky, RK Krishnamurthy & PR Mukund (eds), Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002., 1158094, Proceedings of the Annual IEEE International ASIC Conference and Exhibit, vol. 2002-January, Institute of Electrical and Electronics Engineers Inc., pp. 411-415, 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002, Rochester, United States, 9/25/02. https://doi.org/10.1109/ASIC.2002.1158094

Cao Y, Gupta P, Kahng AB, Sylvester D, Yang J. Design sensitivities to variability: Extrapolations and assessments in nanometer VLSI. In Chickanosky J, Krishnamurthy RK, Mukund PR, editors, Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002. Institute of Electrical and Electronics Engineers Inc. 2002. p. 411-415. 1158094. (Proceedings of the Annual IEEE International ASIC Conference and Exhibit). https://doi.org/10.1109/ASIC.2002.1158094

Cao, Y. ; Gupta, P. ; Kahng, A. B. et al. / Design sensitivities to variability : Extrapolations and assessments in nanometer VLSI. Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002. editor / John Chickanosky ; Ram K. Krishnamurthy ; P.R. Mukund. Institute of Electrical and Electronics Engineers Inc., 2002. pp. 411-415 (Proceedings of the Annual IEEE International ASIC Conference and Exhibit).

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abstract = "We propose a new framework for assessing (1) the impact of process variation on circuit performance and product value, and (2) the respective returns on investment for alternative process improvements. Elements of our framework include accurate device models and circuit simulation, along with Monte-Carlo analyses, to estimate parametric yields. We evaluate the merits of taking into account such previously unconsidered phenomena as correlations among process parameters. We also evaluate the impact of process variation with respect to such relevant metrics as parametric yield at selling point, and amount of required design guardbanding. Our experimental results yield insights into the scaling of process variation impacts through the next two ITRS technology nodes.",

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AB - We propose a new framework for assessing (1) the impact of process variation on circuit performance and product value, and (2) the respective returns on investment for alternative process improvements. Elements of our framework include accurate device models and circuit simulation, along with Monte-Carlo analyses, to estimate parametric yields. We evaluate the merits of taking into account such previously unconsidered phenomena as correlations among process parameters. We also evaluate the impact of process variation with respect to such relevant metrics as parametric yield at selling point, and amount of required design guardbanding. Our experimental results yield insights into the scaling of process variation impacts through the next two ITRS technology nodes.

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Design sensitivities to variability: Extrapolations and assessments in nanometer VLSI

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