Design sensitivities to variability: Extrapolations and assessments in nanometer VLSI

Yu Cao; P. Gupta; A. B. Kahng; D. Sylvester; J. Yang

doi:10.1109/ASIC.2002.1158094

Design sensitivities to variability: Extrapolations and assessments in nanometer VLSI

Yu Cao, P. Gupta, A. B. Kahng, D. Sylvester, J. Yang

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

71 Scopus citations

Abstract

We propose a new framework for assessing (1) the impact of process variation on circuit performance and product value, and (2) the respective returns on investment for alternative process improvements. Elements of our framework include accurate device models and circuit simulation, along with Monte-Carlo analyses, to estimate parametric yields. We evaluate the merits of taking into account such previously unconsidered phenomena as correlations among process parameters. We also evaluate the impact of process variation with respect to such relevant metrics as parametric yield at selling point, and amount of required design guardbanding. Our experimental results yield insights into the scaling of process variation impacts through the next two ITRS technology nodes.

Original language	English (US)
Title of host publication	Proceedings of the Annual IEEE International ASIC Conference and Exhibit
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	411-415
Number of pages	5
Volume	2002-January
ISBN (Print)	0780374940
DOIs	https://doi.org/10.1109/ASIC.2002.1158094
State	Published - 2002
Externally published	Yes
Event	15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002 - Rochester, United States Duration: Sep 25 2002 → Sep 28 2002

Other

Other	15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002
Country	United States
City	Rochester
Period	9/25/02 → 9/28/02

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/ASIC.2002.1158094

Fingerprint Dive into the research topics of 'Design sensitivities to variability: Extrapolations and assessments in nanometer VLSI'. Together they form a unique fingerprint.

Cite this

Cao, Y., Gupta, P., Kahng, A. B., Sylvester, D., & Yang, J. (2002). Design sensitivities to variability: Extrapolations and assessments in nanometer VLSI. In Proceedings of the Annual IEEE International ASIC Conference and Exhibit (Vol. 2002-January, pp. 411-415). [1158094] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASIC.2002.1158094

Design sensitivities to variability : Extrapolations and assessments in nanometer VLSI. / Cao, Yu; Gupta, P.; Kahng, A. B.; Sylvester, D.; Yang, J.

Proceedings of the Annual IEEE International ASIC Conference and Exhibit. Vol. 2002-January Institute of Electrical and Electronics Engineers Inc., 2002. p. 411-415 1158094.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Cao, Y, Gupta, P, Kahng, AB, Sylvester, D & Yang, J 2002, Design sensitivities to variability: Extrapolations and assessments in nanometer VLSI. in Proceedings of the Annual IEEE International ASIC Conference and Exhibit. vol. 2002-January, 1158094, Institute of Electrical and Electronics Engineers Inc., pp. 411-415, 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002, Rochester, United States, 9/25/02. https://doi.org/10.1109/ASIC.2002.1158094

@inproceedings{ed04e33dc28e42bfa4e17b65c806137f,

title = "Design sensitivities to variability: Extrapolations and assessments in nanometer VLSI",

abstract = "We propose a new framework for assessing (1) the impact of process variation on circuit performance and product value, and (2) the respective returns on investment for alternative process improvements. Elements of our framework include accurate device models and circuit simulation, along with Monte-Carlo analyses, to estimate parametric yields. We evaluate the merits of taking into account such previously unconsidered phenomena as correlations among process parameters. We also evaluate the impact of process variation with respect to such relevant metrics as parametric yield at selling point, and amount of required design guardbanding. Our experimental results yield insights into the scaling of process variation impacts through the next two ITRS technology nodes.",

author = "Yu Cao and P. Gupta and Kahng, {A. B.} and D. Sylvester and J. Yang",

year = "2002",

doi = "10.1109/ASIC.2002.1158094",

language = "English (US)",

isbn = "0780374940",

volume = "2002-January",

pages = "411--415",

booktitle = "Proceedings of the Annual IEEE International ASIC Conference and Exhibit",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002 ; Conference date: 25-09-2002 Through 28-09-2002",

}

TY - GEN

T1 - Design sensitivities to variability

T2 - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002

AU - Cao, Yu

AU - Gupta, P.

AU - Kahng, A. B.

AU - Sylvester, D.

AU - Yang, J.

PY - 2002

Y1 - 2002

N2 - We propose a new framework for assessing (1) the impact of process variation on circuit performance and product value, and (2) the respective returns on investment for alternative process improvements. Elements of our framework include accurate device models and circuit simulation, along with Monte-Carlo analyses, to estimate parametric yields. We evaluate the merits of taking into account such previously unconsidered phenomena as correlations among process parameters. We also evaluate the impact of process variation with respect to such relevant metrics as parametric yield at selling point, and amount of required design guardbanding. Our experimental results yield insights into the scaling of process variation impacts through the next two ITRS technology nodes.

AB - We propose a new framework for assessing (1) the impact of process variation on circuit performance and product value, and (2) the respective returns on investment for alternative process improvements. Elements of our framework include accurate device models and circuit simulation, along with Monte-Carlo analyses, to estimate parametric yields. We evaluate the merits of taking into account such previously unconsidered phenomena as correlations among process parameters. We also evaluate the impact of process variation with respect to such relevant metrics as parametric yield at selling point, and amount of required design guardbanding. Our experimental results yield insights into the scaling of process variation impacts through the next two ITRS technology nodes.

UR - http://www.scopus.com/inward/record.url?scp=84949480508&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84949480508&partnerID=8YFLogxK

U2 - 10.1109/ASIC.2002.1158094

DO - 10.1109/ASIC.2002.1158094

M3 - Conference contribution

AN - SCOPUS:84949480508

SN - 0780374940

VL - 2002-January

SP - 411

EP - 415

BT - Proceedings of the Annual IEEE International ASIC Conference and Exhibit

PB - Institute of Electrical and Electronics Engineers Inc.

Y2 - 25 September 2002 through 28 September 2002

ER -