Abstract
We propose a new framework for assessing (1) the impact of process variation on circuit performance and product value, and (2) the respective returns on investment for alternative process improvements. Elements of our framework include accurate device models and circuit simulation, along with Monte-Carlo analyses, to estimate parametric yields. We evaluate the merits of taking into account such previously unconsidered phenomena as correlations among process parameters. We also evaluate the impact of process variation with respect to such relevant metrics as parametric yield at selling point, and amount of required design guardbanding. Our experimental results yield insights into the scaling of process variation impacts through the next two ITRS technology nodes.
Original language | English (US) |
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Title of host publication | Proceedings of the Annual IEEE International ASIC Conference and Exhibit |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 411-415 |
Number of pages | 5 |
Volume | 2002-January |
ISBN (Print) | 0780374940 |
DOIs | |
State | Published - 2002 |
Externally published | Yes |
Event | 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002 - Rochester, United States Duration: Sep 25 2002 → Sep 28 2002 |
Other
Other | 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002 |
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Country | United States |
City | Rochester |
Period | 9/25/02 → 9/28/02 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering