This article explores the use of threshold logic for reducing the power, delay, and/or area of digital logic circuits. We first describe the architecture of a differential threshold logic gate (TLG) using conventional MOSFETs. A TLG of a given number of inputs can be configured to realize a set of threshold functions by simply connecting the appropriate signals to its inputs. One characteristic of the proposed architecture for a TLG is the increased sensitivity to process variations (device mismatch) and noise. Problems due to device mismatch can be mitigated by proper cell design and optimization. The increased sensitivity to noise makes it difficult to scale the supply voltage of a TLG. We show a simple solution which involves integrating RRAMs within the TLG circuit, to achieve robust, low voltage and energy efficient operation. The third circuit implementation referred to as a spintronic threshold logic (STL) cell uses an STT-MTJ device as a intrinsic threshold logic gate. An STL cell is an very compact structure that can realize a large number of threshold functions, many of which would require a multilevel network of conventional CMOS logic gates.