TY - GEN
T1 - Design of threshold logic gates using emerging devices
AU - Vrudhula, Sarma
AU - Kulkami, Niranjan
AU - Yang, Jinghua
N1 - Publisher Copyright:
© 2015 IEEE.
PY - 2015/7/27
Y1 - 2015/7/27
N2 - This article explores the use of threshold logic for reducing the power, delay, and/or area of digital logic circuits. We first describe the architecture of a differential threshold logic gate (TLG) using conventional MOSFETs. A TLG of a given number of inputs can be configured to realize a set of threshold functions by simply connecting the appropriate signals to its inputs. One characteristic of the proposed architecture for a TLG is the increased sensitivity to process variations (device mismatch) and noise. Problems due to device mismatch can be mitigated by proper cell design and optimization. The increased sensitivity to noise makes it difficult to scale the supply voltage of a TLG. We show a simple solution which involves integrating RRAMs within the TLG circuit, to achieve robust, low voltage and energy efficient operation. The third circuit implementation referred to as a spintronic threshold logic (STL) cell uses an STT-MTJ device as a intrinsic threshold logic gate. An STL cell is an very compact structure that can realize a large number of threshold functions, many of which would require a multilevel network of conventional CMOS logic gates.
AB - This article explores the use of threshold logic for reducing the power, delay, and/or area of digital logic circuits. We first describe the architecture of a differential threshold logic gate (TLG) using conventional MOSFETs. A TLG of a given number of inputs can be configured to realize a set of threshold functions by simply connecting the appropriate signals to its inputs. One characteristic of the proposed architecture for a TLG is the increased sensitivity to process variations (device mismatch) and noise. Problems due to device mismatch can be mitigated by proper cell design and optimization. The increased sensitivity to noise makes it difficult to scale the supply voltage of a TLG. We show a simple solution which involves integrating RRAMs within the TLG circuit, to achieve robust, low voltage and energy efficient operation. The third circuit implementation referred to as a spintronic threshold logic (STL) cell uses an STT-MTJ device as a intrinsic threshold logic gate. An STL cell is an very compact structure that can realize a large number of threshold functions, many of which would require a multilevel network of conventional CMOS logic gates.
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U2 - 10.1109/ISCAS.2015.7168648
DO - 10.1109/ISCAS.2015.7168648
M3 - Conference contribution
AN - SCOPUS:84946231823
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 373
EP - 376
BT - 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - IEEE International Symposium on Circuits and Systems, ISCAS 2015
Y2 - 24 May 2015 through 27 May 2015
ER -