Abstract
Recently, 2-D cross-point array of resistive random access memory (RRAM) has been proposed for implementing the weighted sum and weight update operations to accelerate the neuro-inspired learning algorithms on chip. This paper aims to extend such 2-D cross-point array to 3-D vertical array for storing and computing the large-scale weight matrices in the neural network. Considering the fabrication and 3-D integration of analog synapses (i.e., multilevel RRAM devices) are premature at this stage, we propose using today's available digital or binary RRAM devices for implementing a ternary neural network, which aggressively reduces the weight precision to ternary levels (+1, 0,-1) for the weighted sum in both feedforward and backward inference, while the multiple 3-D layers could serve for accumulating the small errors in a higher precision format for weight update. Compared to the 2-D implementation, the proposed 3-D vertical implementation shows larger read/write margin for weighted sum/weight update, smaller latency, and energy consumption for weight update. This paper demonstrates the attractiveness for building a monolithic 3-D neuromorphic hardware platform.
Original language | English (US) |
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Article number | 7917308 |
Pages (from-to) | 2721-2727 |
Number of pages | 7 |
Journal | IEEE Transactions on Electron Devices |
Volume | 64 |
Issue number | 6 |
DOIs | |
State | Published - Jun 2017 |
Keywords
- Monolithic 3-D integration
- multilayer perceptron (MLP)
- neural network
- neuromorphiccomputing
- resistive memory
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering