Design of NoC for SoC with multiple use cases requiring guaranteed performance

Glenn Leary; Karam S. Chatha

doi:10.1109/VLSI.Design.2010.73

Design of NoC for SoC with multiple use cases requiring guaranteed performance

Glenn Leary, Karam S. Chatha

Computing and Augmented Intelligence, School of (IAFSE-SCAI)

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

5 Scopus citations

Abstract

Many SoC architectures aimed at the multimedia domain support multiple use cases where only a subset of the applications is active at any time. Further, each multimedia application itself poses strict constraints on core-to-core communication latency. This paper presents an approach for automated synthesis of NoC architectures for such an SoC. We evaluated our design approach through comparisons with two existing techniques aimed at generating best effort and guaranteed throughput designs. Designs generated by our approach showed a marked improvement in both power consumption (12.3% decrease) and resource requirements (12.9% decrease) in comparison to the best effort NoC design approach. In comparison to the existing guaranteed throughput design approach our designs can guarantee core-to-core latency while consuming less power (8.1% decrease) and resources (7.9% decrease).

Original language	English (US)
Title of host publication	VLSi Design 2010 - 23rd International Conference on VLSI Design, Held jointly with 9th International Conference on Embedded Systems
Pages	200-205
Number of pages	6
DOIs	https://doi.org/10.1109/VLSI.Design.2010.73
State	Published - 2010
Event	23rd International Conference on VLSI Design, Held jointly with 9th International Conference on Embedded Systems, VLSi Design 2010 - Bangalore, India Duration: Jan 3 2010 → Jan 7 2010

Publication series

Name	Proceedings of the IEEE International Conference on VLSI Design
ISSN (Print)	1063-9667

Other

Other	23rd International Conference on VLSI Design, Held jointly with 9th International Conference on Embedded Systems, VLSi Design 2010
Country/Territory	India
City	Bangalore
Period	1/3/10 → 1/7/10

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/VLSI.Design.2010.73

Cite this

Leary, G., & Chatha, K. S. (2010). Design of NoC for SoC with multiple use cases requiring guaranteed performance. In VLSi Design 2010 - 23rd International Conference on VLSI Design, Held jointly with 9th International Conference on Embedded Systems (pp. 200-205). Article 5401355 (Proceedings of the IEEE International Conference on VLSI Design). https://doi.org/10.1109/VLSI.Design.2010.73

Design of NoC for SoC with multiple use cases requiring guaranteed performance. / Leary, Glenn; Chatha, Karam S.
VLSi Design 2010 - 23rd International Conference on VLSI Design, Held jointly with 9th International Conference on Embedded Systems. 2010. p. 200-205 5401355 (Proceedings of the IEEE International Conference on VLSI Design).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Leary, G & Chatha, KS 2010, Design of NoC for SoC with multiple use cases requiring guaranteed performance. in VLSi Design 2010 - 23rd International Conference on VLSI Design, Held jointly with 9th International Conference on Embedded Systems., 5401355, Proceedings of the IEEE International Conference on VLSI Design, pp. 200-205, 23rd International Conference on VLSI Design, Held jointly with 9th International Conference on Embedded Systems, VLSi Design 2010, Bangalore, India, 1/3/10. https://doi.org/10.1109/VLSI.Design.2010.73

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Design of NoC for SoC with multiple use cases requiring guaranteed performance

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