Design of NoC for SoC with multiple use cases requiring guaranteed performance

Glenn Leary, Karam S. Chatha

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

Many SoC architectures aimed at the multimedia domain support multiple use cases where only a subset of the applications is active at any time. Further, each multimedia application itself poses strict constraints on core-to-core communication latency. This paper presents an approach for automated synthesis of NoC architectures for such an SoC. We evaluated our design approach through comparisons with two existing techniques aimed at generating best effort and guaranteed throughput designs. Designs generated by our approach showed a marked improvement in both power consumption (12.3% decrease) and resource requirements (12.9% decrease) in comparison to the best effort NoC design approach. In comparison to the existing guaranteed throughput design approach our designs can guarantee core-to-core latency while consuming less power (8.1% decrease) and resources (7.9% decrease).

Original languageEnglish (US)
Title of host publicationProceedings of the IEEE International Conference on VLSI Design
Pages200-205
Number of pages6
DOIs
StatePublished - 2010
Event23rd International Conference on VLSI Design, Held jointly with 9th International Conference on Embedded Systems, VLSi Design 2010 - Bangalore, India
Duration: Jan 3 2010Jan 7 2010

Other

Other23rd International Conference on VLSI Design, Held jointly with 9th International Conference on Embedded Systems, VLSi Design 2010
CountryIndia
CityBangalore
Period1/3/101/7/10

Fingerprint

Throughput
Network-on-chip
System-on-chip
Electric power utilization
Communication

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture

Cite this

Leary, G., & Chatha, K. S. (2010). Design of NoC for SoC with multiple use cases requiring guaranteed performance. In Proceedings of the IEEE International Conference on VLSI Design (pp. 200-205). [5401355] https://doi.org/10.1109/VLSI.Design.2010.73

Design of NoC for SoC with multiple use cases requiring guaranteed performance. / Leary, Glenn; Chatha, Karam S.

Proceedings of the IEEE International Conference on VLSI Design. 2010. p. 200-205 5401355.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Leary, G & Chatha, KS 2010, Design of NoC for SoC with multiple use cases requiring guaranteed performance. in Proceedings of the IEEE International Conference on VLSI Design., 5401355, pp. 200-205, 23rd International Conference on VLSI Design, Held jointly with 9th International Conference on Embedded Systems, VLSi Design 2010, Bangalore, India, 1/3/10. https://doi.org/10.1109/VLSI.Design.2010.73
Leary G, Chatha KS. Design of NoC for SoC with multiple use cases requiring guaranteed performance. In Proceedings of the IEEE International Conference on VLSI Design. 2010. p. 200-205. 5401355 https://doi.org/10.1109/VLSI.Design.2010.73
Leary, Glenn ; Chatha, Karam S. / Design of NoC for SoC with multiple use cases requiring guaranteed performance. Proceedings of the IEEE International Conference on VLSI Design. 2010. pp. 200-205
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