Design of network-on-chip architectures with a genetic algorithm-based technique

Glenn Leary, Krishnan Srinivasan, Krishna Mehta, Karam S. Chatha

Research output: Contribution to journalArticle

51 Citations (Scopus)

Abstract

The network-on-chip (NoC) design problem requires the generation of a power and resource efficient interconnection architecture that can support the communication requirements for the SoC with the desired performance. This paper presents a genetic algorithm-based automated design technique that synthesizes an application specific NoC topology and routes the communication traces on the interconnection network. The technique operates on the system-level floorplan of the system on chip (SoC) and accounts for the power consumption in the physical links and the routers. The design technique solves a multi-objective problem of minimizing the power consumption and the router resources. It generates a Pareto curve of the solution set, such that each point in the curve represents a tradeoff between power consumption and associated number of NoC routers. The performance and quality of solutions produced by the technique are evaluated by experimentation with benchmark applications and comparisons with existing approaches.

Original languageEnglish (US)
Article number4773141
Pages (from-to)674-687
Number of pages14
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume17
Issue number5
DOIs
StatePublished - May 2009

Fingerprint

Routers
Electric power utilization
Genetic algorithms
Communication
Topology
Network-on-chip
System-on-chip

Keywords

  • Design automation
  • Genetic algorithms
  • Network-on-chip (NoC)
  • Routing

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture
  • Software

Cite this

Design of network-on-chip architectures with a genetic algorithm-based technique. / Leary, Glenn; Srinivasan, Krishnan; Mehta, Krishna; Chatha, Karam S.

In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 17, No. 5, 4773141, 05.2009, p. 674-687.

Research output: Contribution to journalArticle

Leary, Glenn ; Srinivasan, Krishnan ; Mehta, Krishna ; Chatha, Karam S. / Design of network-on-chip architectures with a genetic algorithm-based technique. In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2009 ; Vol. 17, No. 5. pp. 674-687.
@article{aed8b26d96fa42de8e584a63d930988a,
title = "Design of network-on-chip architectures with a genetic algorithm-based technique",
abstract = "The network-on-chip (NoC) design problem requires the generation of a power and resource efficient interconnection architecture that can support the communication requirements for the SoC with the desired performance. This paper presents a genetic algorithm-based automated design technique that synthesizes an application specific NoC topology and routes the communication traces on the interconnection network. The technique operates on the system-level floorplan of the system on chip (SoC) and accounts for the power consumption in the physical links and the routers. The design technique solves a multi-objective problem of minimizing the power consumption and the router resources. It generates a Pareto curve of the solution set, such that each point in the curve represents a tradeoff between power consumption and associated number of NoC routers. The performance and quality of solutions produced by the technique are evaluated by experimentation with benchmark applications and comparisons with existing approaches.",
keywords = "Design automation, Genetic algorithms, Network-on-chip (NoC), Routing",
author = "Glenn Leary and Krishnan Srinivasan and Krishna Mehta and Chatha, {Karam S.}",
year = "2009",
month = "5",
doi = "10.1109/TVLSI.2008.2011205",
language = "English (US)",
volume = "17",
pages = "674--687",
journal = "IEEE Transactions on Very Large Scale Integration (VLSI) Systems",
issn = "1063-8210",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "5",

}

TY - JOUR

T1 - Design of network-on-chip architectures with a genetic algorithm-based technique

AU - Leary, Glenn

AU - Srinivasan, Krishnan

AU - Mehta, Krishna

AU - Chatha, Karam S.

PY - 2009/5

Y1 - 2009/5

N2 - The network-on-chip (NoC) design problem requires the generation of a power and resource efficient interconnection architecture that can support the communication requirements for the SoC with the desired performance. This paper presents a genetic algorithm-based automated design technique that synthesizes an application specific NoC topology and routes the communication traces on the interconnection network. The technique operates on the system-level floorplan of the system on chip (SoC) and accounts for the power consumption in the physical links and the routers. The design technique solves a multi-objective problem of minimizing the power consumption and the router resources. It generates a Pareto curve of the solution set, such that each point in the curve represents a tradeoff between power consumption and associated number of NoC routers. The performance and quality of solutions produced by the technique are evaluated by experimentation with benchmark applications and comparisons with existing approaches.

AB - The network-on-chip (NoC) design problem requires the generation of a power and resource efficient interconnection architecture that can support the communication requirements for the SoC with the desired performance. This paper presents a genetic algorithm-based automated design technique that synthesizes an application specific NoC topology and routes the communication traces on the interconnection network. The technique operates on the system-level floorplan of the system on chip (SoC) and accounts for the power consumption in the physical links and the routers. The design technique solves a multi-objective problem of minimizing the power consumption and the router resources. It generates a Pareto curve of the solution set, such that each point in the curve represents a tradeoff between power consumption and associated number of NoC routers. The performance and quality of solutions produced by the technique are evaluated by experimentation with benchmark applications and comparisons with existing approaches.

KW - Design automation

KW - Genetic algorithms

KW - Network-on-chip (NoC)

KW - Routing

UR - http://www.scopus.com/inward/record.url?scp=67349133523&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=67349133523&partnerID=8YFLogxK

U2 - 10.1109/TVLSI.2008.2011205

DO - 10.1109/TVLSI.2008.2011205

M3 - Article

VL - 17

SP - 674

EP - 687

JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

SN - 1063-8210

IS - 5

M1 - 4773141

ER -