Design of HM2P—a Hierarchical Multimicroprocessor for General-Purpose Applications

This paper presents a tree-structured multiprocessor called the hierarchical multimicroprocessor (HM2p), each node of which is composed of a cluster of processor modules (PM's), common memory, DMA interface, switches, communication lines, and a data processor associated with it. The HM2p consists of two different hierarchies, one for data processing and the other for data distribution, which provide clean, structured separation between processing components and user interface components. There are two levels of interprocessor communications in the HM2p, an implementation of which is developed with the monitor concept. By examining the access pattern of shared hardware resources, we have modeled the performance of the HM2p as a multichain closed queueing network. Using this queueing model, the performance falloffs due to shared hardware (e.g., processors, memory, and I/O devices) are also analyzed, and the optimum number of processors in each cluster is then determined.