Design of Diagnosable Iterative Arrays

One- and two-dimensional iterative arrays of identical cells are becoming more important in the design of digital systems using large-scale integrated circuits because of the advantages that they provide in design, fabrication, and testing. Since arrays containing hundreds or thousands of gates on one chip are now considered possible, the task of finding procedures for the testing of such arrays from their edges is of concern to both the users and the manufacturers. The iterative nature of cellular arrays sometimes makes it possible to derive test schedules of reasonable length. In this paper, we present some efficient methods for modifying iterative logic arrays to make them “easily diagnosable” and for deriving test schedules for these arrays. The arrays treated are one- and two-dimensional arrays of combinational logic in which we assume that at most one typical cell is faulty. The techniques presented are also applicable to some arrays having cells which contain a small amount of storage.