Design of concurrent test hardware for linear analog circuits with constrained hardware overhead

Sule Ozev, Alex Orailoglu

Research output: Contribution to journalArticle

4 Citations (Scopus)

Abstract

Concurrent detection of failures in analog circuits is becoming increasingly more important as safety-critical systems become more widespread. A methodology for automatic design of concurrent failure detection circuitry for linear analog systems is discussed in this paper. The desired hardware bound is specified as a constraint; the methodology aims at providing coverage in terms of all the circuit components while minimizing the loading overhead by reducing the number of internal circuit nodes that need to be tapped. Parameter tolerances are incorporated through either statistical or mathematical analysis to determine the threshold for failure alarm.

Original languageEnglish (US)
Pages (from-to)756-765
Number of pages10
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume12
Issue number7
DOIs
StatePublished - Jul 2004
Externally publishedYes

Fingerprint

Analog circuits
Hardware
Networks (circuits)

Keywords

  • Analog testing
  • Design automation
  • Online error detection

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture

Cite this

Design of concurrent test hardware for linear analog circuits with constrained hardware overhead. / Ozev, Sule; Orailoglu, Alex.

In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 12, No. 7, 07.2004, p. 756-765.

Research output: Contribution to journalArticle

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