Design of an automatic target recognition algorithm on the IBM cell broadband engine

Weijia Che, Karam S. Chatha

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The paper presents the design of an Automatic Target Recognition (ATR) algorithm on the IBM Cell Broadband Engine (Cell BE). The implementation utilizes several optimizations that exploit both the specific algorithm constructs of the ATR and the architectural features of the Cell processor. We discuss a total of 8 optimizations and present performance improvements achieved by their application. The latency of the Cell BE implementation of the ATR algorithm is 0.070 seconds on the Sony PlayStation3 (PS3) platform. The achieved performance is more than 25 times faster than the fully optimized PowerPC implementation and almost 20 times faster than our best efforts on a Pentium4 CPU.

Original languageEnglish (US)
Title of host publicationASAP 10 - 21st IEEE International Conference on Application-Specific Systems, Architectures and Processors, Conference Proceedings
Pages21-28
Number of pages8
DOIs
StatePublished - 2010
Event21st IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2010 - Rennes, France
Duration: Jul 7 2010Jul 9 2010

Publication series

NameProceedings of the International Conference on Application-Specific Systems, Architectures and Processors
ISSN (Print)1063-6862

Other

Other21st IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2010
Country/TerritoryFrance
CityRennes
Period7/7/107/9/10

Keywords

  • Automatic target recognition
  • IBM Cell BE

ASJC Scopus subject areas

  • Hardware and Architecture
  • Computer Networks and Communications

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