Design of a robust, high performance standard cell threshold logic family for DSM technology

Samuel Leshner, Niranjan Kulkarni, Sarma Vrudhula, Krzysztof Berezowski

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Scopus citations

Abstract

This paper presents the threshold logic latch (TLL), which provides a high performance, low power alternative to traditional CMOS logic networks. TLL is highly robust, even in deep sub-micron technology nodes. Experimental results obtained from simulation of a commercial 65 nm low power process demonstrate a static noise margin up to an order of magnitude greater than those of existing implementations of threshold logic. Examples of automated synthesis of pipelined multipliers using a combination of standard CMOS and a small number of TLL gates are shown through simulation to improve both area and total power by a factor of up to 1.5 and reduce leakage power by a factor of up to 2.3.

Original languageEnglish (US)
Title of host publication2010 International Conference on Microelectronics, ICM'10
Pages52-55
Number of pages4
DOIs
StatePublished - Dec 1 2010
Event2010 International Conference on Microelectronics, ICM'10 - Cairo, Egypt
Duration: Dec 19 2010Dec 22 2010

Publication series

NameProceedings of the International Conference on Microelectronics, ICM

Other

Other2010 International Conference on Microelectronics, ICM'10
CountryEgypt
CityCairo
Period12/19/1012/22/10

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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