Design of a fast and area efficient multi-input muller C-element

Tzyh Yung Wuu, Sarma Vrudhula

Research output: Contribution to journalArticle

34 Citations (Scopus)

Abstract

A multi-input Muller C-element has frequently been used for joining signal transitions or completion time detection self-timed circuits. This paper presents an n-input Muller C-element design which uses the multi-level login design technique and has a symmetric format for any integer n≥ 2. In comparison with series-parallel MOS structure implementations and C-element tree implementations, our design has fewer restrictions in terms of n, less path delay, less delay variance from inputs to output, and less area consumption. Experimental validation in this paper is based on an industrial standard cell library.

Original languageEnglish (US)
Pages (from-to)215-219
Number of pages5
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume1
Issue number2
DOIs
StatePublished - Jun 1993

Fingerprint

Joining
Networks (circuits)

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Design of a fast and area efficient multi-input muller C-element. / Wuu, Tzyh Yung; Vrudhula, Sarma.

In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 1, No. 2, 06.1993, p. 215-219.

Research output: Contribution to journalArticle

@article{6ba3d233af494776920059b7d70b5500,
title = "Design of a fast and area efficient multi-input muller C-element",
abstract = "A multi-input Muller C-element has frequently been used for joining signal transitions or completion time detection self-timed circuits. This paper presents an n-input Muller C-element design which uses the multi-level login design technique and has a symmetric format for any integer n≥ 2. In comparison with series-parallel MOS structure implementations and C-element tree implementations, our design has fewer restrictions in terms of n, less path delay, less delay variance from inputs to output, and less area consumption. Experimental validation in this paper is based on an industrial standard cell library.",
author = "Wuu, {Tzyh Yung} and Sarma Vrudhula",
year = "1993",
month = "6",
doi = "10.1109/92.238414",
language = "English (US)",
volume = "1",
pages = "215--219",
journal = "IEEE Transactions on Very Large Scale Integration (VLSI) Systems",
issn = "1063-8210",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "2",

}

TY - JOUR

T1 - Design of a fast and area efficient multi-input muller C-element

AU - Wuu, Tzyh Yung

AU - Vrudhula, Sarma

PY - 1993/6

Y1 - 1993/6

N2 - A multi-input Muller C-element has frequently been used for joining signal transitions or completion time detection self-timed circuits. This paper presents an n-input Muller C-element design which uses the multi-level login design technique and has a symmetric format for any integer n≥ 2. In comparison with series-parallel MOS structure implementations and C-element tree implementations, our design has fewer restrictions in terms of n, less path delay, less delay variance from inputs to output, and less area consumption. Experimental validation in this paper is based on an industrial standard cell library.

AB - A multi-input Muller C-element has frequently been used for joining signal transitions or completion time detection self-timed circuits. This paper presents an n-input Muller C-element design which uses the multi-level login design technique and has a symmetric format for any integer n≥ 2. In comparison with series-parallel MOS structure implementations and C-element tree implementations, our design has fewer restrictions in terms of n, less path delay, less delay variance from inputs to output, and less area consumption. Experimental validation in this paper is based on an industrial standard cell library.

UR - http://www.scopus.com/inward/record.url?scp=0027612041&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0027612041&partnerID=8YFLogxK

U2 - 10.1109/92.238414

DO - 10.1109/92.238414

M3 - Article

AN - SCOPUS:0027612041

VL - 1

SP - 215

EP - 219

JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

SN - 1063-8210

IS - 2

ER -