Design Limits of In-Memory Computing: Beyond the Crossbar

Gokul Krishnan, Jubin Hazra, Maximilian Liehr, Xiaocong Du, Karsten Beckmann, Rajiv V. Joshi, Nathaniel C. Cady, Yu Cao

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Resistive random-access memory (RRAM)-based in-memory computing (IMC) architecture offers an energy-efficient solution for DNN acceleration. Yet, its performance is limited by device non-idealities, circuit precision, on-chip interconnection, and algorithm properties. Based on statistical data from a fully-integrated 65nm CMOS/RRAM test chip and a cross-layer simulation framework, we show that the IMC system's real bottleneck is not the RRAM device but the analog-to-digital converter (ADC) precision and the stability of DNN models. The results are summarized into a roofline model and demonstrated on CIFAR-10, SVHN, CIFAR-100, and ImageNet, helping understand RRAM-based IMC architectures' design limits.

Original languageEnglish (US)
Title of host publication2021 5th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2021
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728181769
DOIs
StatePublished - Apr 8 2021
Event5th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2021 - Chengdu, China
Duration: Apr 8 2021Apr 11 2021

Publication series

Name2021 5th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2021

Conference

Conference5th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2021
Country/TerritoryChina
CityChengdu
Period4/8/214/11/21

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Industrial and Manufacturing Engineering
  • Electronic, Optical and Magnetic Materials

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