TY - GEN
T1 - Design Limits of In-Memory Computing
T2 - 5th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2021
AU - Krishnan, Gokul
AU - Hazra, Jubin
AU - Liehr, Maximilian
AU - Du, Xiaocong
AU - Beckmann, Karsten
AU - Joshi, Rajiv V.
AU - Cady, Nathaniel C.
AU - Cao, Yu
N1 - Funding Information:
This work was supported in part by the Semiconductor Research Corporation (SRC) and DARPA, the National Science Foundation (NSF) under CCF-1715443, and the Air Force Research Laboratory award #FA8750-19-1-0014.
Publisher Copyright:
© 2021 IEEE.
PY - 2021/4/8
Y1 - 2021/4/8
N2 - Resistive random-access memory (RRAM)-based in-memory computing (IMC) architecture offers an energy-efficient solution for DNN acceleration. Yet, its performance is limited by device non-idealities, circuit precision, on-chip interconnection, and algorithm properties. Based on statistical data from a fully-integrated 65nm CMOS/RRAM test chip and a cross-layer simulation framework, we show that the IMC system's real bottleneck is not the RRAM device but the analog-to-digital converter (ADC) precision and the stability of DNN models. The results are summarized into a roofline model and demonstrated on CIFAR-10, SVHN, CIFAR-100, and ImageNet, helping understand RRAM-based IMC architectures' design limits.
AB - Resistive random-access memory (RRAM)-based in-memory computing (IMC) architecture offers an energy-efficient solution for DNN acceleration. Yet, its performance is limited by device non-idealities, circuit precision, on-chip interconnection, and algorithm properties. Based on statistical data from a fully-integrated 65nm CMOS/RRAM test chip and a cross-layer simulation framework, we show that the IMC system's real bottleneck is not the RRAM device but the analog-to-digital converter (ADC) precision and the stability of DNN models. The results are summarized into a roofline model and demonstrated on CIFAR-10, SVHN, CIFAR-100, and ImageNet, helping understand RRAM-based IMC architectures' design limits.
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U2 - 10.1109/EDTM50988.2021.9421057
DO - 10.1109/EDTM50988.2021.9421057
M3 - Conference contribution
AN - SCOPUS:85106507006
T3 - 2021 5th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2021
BT - 2021 5th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2021
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 8 April 2021 through 11 April 2021
ER -