Design guidelines of RRAM based neural-processing-unit

A joint device-circuit-algorithm analysis

Wenqiang Zhang, Xiaochen Peng, Huaqiang Wu, Bin Gao, Hu He, Youhui Zhang, Shimeng Yu, He Qian

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

RRAM based neural-processing-unit (NPU) is emerging for processing general purpose machine intelligence algorithms with ultra-high energy efficiency, while the imperfections of the analog devices and cross-point arrays make the practical application more complicated. In order to improve accuracy and robustness of the NPU, device-circuit-algorithm codesign with consideration of underlying device and array characteristics should outperform the optimization of individual device or algorithm. In this work, we provide a joint device-circuit-algorithm analysis and propose the corresponding design guidelines. Key innovations include: 1) An end-to-end simulator for RRAM NPU is developed with an integrated framework from device to algorithm. 2) The complete design of circuit and architecture for RRAM NPU is provided to make the analysis much close to the real prototype. 3) A large-scale neural network as well as other general-purpose networks are processed for the study of device-circuit interaction. 4) Accuracy loss from non-idealities of RRAM, such as I-V nonlinearity, noises of analog resistance levels, voltage-drop for interconnect, ADC/DAC precision, are evaluated for the NPU design.

Original languageEnglish (US)
Title of host publicationProceedings of the 56th Annual Design Automation Conference 2019, DAC 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781450367257
DOIs
StatePublished - Jun 2 2019
Event56th Annual Design Automation Conference, DAC 2019 - Las Vegas, United States
Duration: Jun 2 2019Jun 6 2019

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0738-100X

Conference

Conference56th Annual Design Automation Conference, DAC 2019
CountryUnited States
CityLas Vegas
Period6/2/196/6/19

Fingerprint

Algorithm Analysis
Unit
Networks (circuits)
Processing
Analogue
Co-design
Imperfections
Interconnect
Energy efficiency
Design
RRAM
Energy Efficiency
Innovation
Simulators
High Efficiency
High Energy
Simulator
Neural networks
Voltage
Defects

ASJC Scopus subject areas

  • Computer Science Applications
  • Control and Systems Engineering
  • Electrical and Electronic Engineering
  • Modeling and Simulation

Cite this

Zhang, W., Peng, X., Wu, H., Gao, B., He, H., Zhang, Y., ... Qian, H. (2019). Design guidelines of RRAM based neural-processing-unit: A joint device-circuit-algorithm analysis. In Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019 [a140] (Proceedings - Design Automation Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1145/3316781.3317797

Design guidelines of RRAM based neural-processing-unit : A joint device-circuit-algorithm analysis. / Zhang, Wenqiang; Peng, Xiaochen; Wu, Huaqiang; Gao, Bin; He, Hu; Zhang, Youhui; Yu, Shimeng; Qian, He.

Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019. Institute of Electrical and Electronics Engineers Inc., 2019. a140 (Proceedings - Design Automation Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Zhang, W, Peng, X, Wu, H, Gao, B, He, H, Zhang, Y, Yu, S & Qian, H 2019, Design guidelines of RRAM based neural-processing-unit: A joint device-circuit-algorithm analysis. in Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019., a140, Proceedings - Design Automation Conference, Institute of Electrical and Electronics Engineers Inc., 56th Annual Design Automation Conference, DAC 2019, Las Vegas, United States, 6/2/19. https://doi.org/10.1145/3316781.3317797
Zhang W, Peng X, Wu H, Gao B, He H, Zhang Y et al. Design guidelines of RRAM based neural-processing-unit: A joint device-circuit-algorithm analysis. In Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019. Institute of Electrical and Electronics Engineers Inc. 2019. a140. (Proceedings - Design Automation Conference). https://doi.org/10.1145/3316781.3317797
Zhang, Wenqiang ; Peng, Xiaochen ; Wu, Huaqiang ; Gao, Bin ; He, Hu ; Zhang, Youhui ; Yu, Shimeng ; Qian, He. / Design guidelines of RRAM based neural-processing-unit : A joint device-circuit-algorithm analysis. Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019. Institute of Electrical and Electronics Engineers Inc., 2019. (Proceedings - Design Automation Conference).
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