Design flows and collateral for the ASAP7 7nm FinFET predictive process design kit

Lawrence T. Clark, Vinay Vashishtha, David M. Harris, Samuel Dietrich, Zunyan Wang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

Educators and researchers exploring integrated circuit design methods need models and design flows for advanced integrated circuit processes. As commercial processes have become highly proprietary, predictive technology models fill the gap. This work describes a design flow for ASAP7, the first 7 nm FinFET PDK, including schematic and layout entry, library characterization, synthesis, placement and routing, parasitic extraction, and HSPICE simulation.

Original languageEnglish (US)
Title of host publication2017 IEEE International Conference on Microelectronic Systems Education, MSE 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1-4
Number of pages4
ISBN (Electronic)9781509064311
DOIs
StatePublished - Jun 8 2017
Event2017 IEEE International Conference on Microelectronic Systems Education, MSE 2017 - Banff, Canada
Duration: May 11 2017May 12 2017

Other

Other2017 IEEE International Conference on Microelectronic Systems Education, MSE 2017
CountryCanada
CityBanff
Period5/11/175/12/17

Keywords

  • design flow
  • FinFETs
  • predictive technology model

ASJC Scopus subject areas

  • Education
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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  • Cite this

    Clark, L. T., Vashishtha, V., Harris, D. M., Dietrich, S., & Wang, Z. (2017). Design flows and collateral for the ASAP7 7nm FinFET predictive process design kit. In 2017 IEEE International Conference on Microelectronic Systems Education, MSE 2017 (pp. 1-4). [7945071] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/MSE.2017.7945071