Abstract
Educators and researchers exploring integrated circuit design methods need models and design flows for advanced integrated circuit processes. As commercial processes have become highly proprietary, predictive technology models fill the gap. This work describes a design flow for ASAP7, the first 7 nm FinFET PDK, including schematic and layout entry, library characterization, synthesis, placement and routing, parasitic extraction, and HSPICE simulation.
Original language | English (US) |
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Title of host publication | 2017 IEEE International Conference on Microelectronic Systems Education, MSE 2017 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 1-4 |
Number of pages | 4 |
ISBN (Electronic) | 9781509064311 |
DOIs | |
State | Published - Jun 8 2017 |
Event | 2017 IEEE International Conference on Microelectronic Systems Education, MSE 2017 - Banff, Canada Duration: May 11 2017 → May 12 2017 |
Other
Other | 2017 IEEE International Conference on Microelectronic Systems Education, MSE 2017 |
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Country/Territory | Canada |
City | Banff |
Period | 5/11/17 → 5/12/17 |
Keywords
- design flow
- FinFETs
- predictive technology model
ASJC Scopus subject areas
- Education
- Hardware and Architecture
- Electrical and Electronic Engineering