@inproceedings{7a63106ee3034b14960709001477ebfe,
title = "Design benchmarking to 7nm with FinFET predictive technology models",
abstract = "The coming ten years promise great changes in silicon technology, with the end of planar bulk CMOS and the rise of interconnect parasitics to true significance. With such shifts in the underlying technology, the simple extrapolation of performance metrics may lead to pronounced prediction errors in design pathfinding. In this work, we utilize newly developed Predictive Technology Models for FinFETs aligned to the 2011 ITRS. Together with predictive interconnect models, we project performance and power landscape for the technology nodes from 20nm to 7nm. We present an overview of models, assess the advantage of FinFET over bulk CMOS devices, benchmark the scaling of critical design metrics, and illustrate major design barriers toward the 7nm node.",
keywords = "beol, finfet, integrated circuits, performance, power, predictive technology models, scaling trends",
author = "Saurabh Sinha and Brian Cline and Greg Yeric and Vikas Chandra and Yu Cao",
year = "2012",
doi = "10.1145/2333660.2333666",
language = "English (US)",
isbn = "9781450312493",
series = "Proceedings of the International Symposium on Low Power Electronics and Design",
pages = "15--20",
booktitle = "ISLPED'12 - Proceedings of the International Symposium on Low Power Electronics and Design",
note = "2012 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED'12 ; Conference date: 30-07-2012 Through 01-08-2012",
}