Design benchmarking to 7nm with FinFET predictive technology models

Saurabh Sinha, Brian Cline, Greg Yeric, Vikas Chandra, Yu Cao

Research output: Chapter in Book/Report/Conference proceedingConference contribution

21 Citations (Scopus)

Abstract

The coming ten years promise great changes in silicon technology, with the end of planar bulk CMOS and the rise of interconnect parasitics to true significance. With such shifts in the underlying technology, the simple extrapolation of performance metrics may lead to pronounced prediction errors in design pathfinding. In this work, we utilize newly developed Predictive Technology Models for FinFETs aligned to the 2011 ITRS. Together with predictive interconnect models, we project performance and power landscape for the technology nodes from 20nm to 7nm. We present an overview of models, assess the advantage of FinFET over bulk CMOS devices, benchmark the scaling of critical design metrics, and illustrate major design barriers toward the 7nm node.

Original languageEnglish (US)
Title of host publicationProceedings of the International Symposium on Low Power Electronics and Design
Pages15-20
Number of pages6
DOIs
StatePublished - 2012
Event2012 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED'12 - Redondo Beach, CA, United States
Duration: Jul 30 2012Aug 1 2012

Other

Other2012 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED'12
CountryUnited States
CityRedondo Beach, CA
Period7/30/128/1/12

Fingerprint

Benchmarking
Extrapolation
Silicon
FinFET

Keywords

  • beol
  • finfet
  • integrated circuits
  • performance
  • power
  • predictive technology models
  • scaling trends

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Sinha, S., Cline, B., Yeric, G., Chandra, V., & Cao, Y. (2012). Design benchmarking to 7nm with FinFET predictive technology models. In Proceedings of the International Symposium on Low Power Electronics and Design (pp. 15-20) https://doi.org/10.1145/2333660.2333666

Design benchmarking to 7nm with FinFET predictive technology models. / Sinha, Saurabh; Cline, Brian; Yeric, Greg; Chandra, Vikas; Cao, Yu.

Proceedings of the International Symposium on Low Power Electronics and Design. 2012. p. 15-20.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Sinha, S, Cline, B, Yeric, G, Chandra, V & Cao, Y 2012, Design benchmarking to 7nm with FinFET predictive technology models. in Proceedings of the International Symposium on Low Power Electronics and Design. pp. 15-20, 2012 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED'12, Redondo Beach, CA, United States, 7/30/12. https://doi.org/10.1145/2333660.2333666
Sinha S, Cline B, Yeric G, Chandra V, Cao Y. Design benchmarking to 7nm with FinFET predictive technology models. In Proceedings of the International Symposium on Low Power Electronics and Design. 2012. p. 15-20 https://doi.org/10.1145/2333660.2333666
Sinha, Saurabh ; Cline, Brian ; Yeric, Greg ; Chandra, Vikas ; Cao, Yu. / Design benchmarking to 7nm with FinFET predictive technology models. Proceedings of the International Symposium on Low Power Electronics and Design. 2012. pp. 15-20
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