TY - GEN
T1 - Design and optimization of strong Physical Unclonable Function (PUF) based on RRAM array
AU - Pang, Yachuan
AU - Wu, Huaqiang
AU - Gao, Bin
AU - Liu, Rui
AU - Wang, Shan
AU - Yu, Shimeng
AU - Chen, An
AU - Qian, He
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2017/6/7
Y1 - 2017/6/7
N2 - Physical Unclonable Function (PUF) based on high-density RRAM array is suitable for hardware security applications. In this work, an RRAM-based strong PUF leveraging random resistance variation is experimentally demonstrated. The number of challenge response pairs increase significantly compared with the previous weak PUF design. The PUF reliability is optimized through extending the resistance distribution, and a novel multiple small SET operation method is utilized to achieve the above purpose. The experimental results show that the intra-HD (intra-chip Hamming distance) reduced from ∼8% to ∼3.5% after using the optimized method. The inter-HD (inter-chip Hamming distance) maintains close to the ideal value 50%.
AB - Physical Unclonable Function (PUF) based on high-density RRAM array is suitable for hardware security applications. In this work, an RRAM-based strong PUF leveraging random resistance variation is experimentally demonstrated. The number of challenge response pairs increase significantly compared with the previous weak PUF design. The PUF reliability is optimized through extending the resistance distribution, and a novel multiple small SET operation method is utilized to achieve the above purpose. The experimental results show that the intra-HD (intra-chip Hamming distance) reduced from ∼8% to ∼3.5% after using the optimized method. The inter-HD (inter-chip Hamming distance) maintains close to the ideal value 50%.
UR - http://www.scopus.com/inward/record.url?scp=85023179949&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85023179949&partnerID=8YFLogxK
U2 - 10.1109/VLSI-TSA.2017.7942473
DO - 10.1109/VLSI-TSA.2017.7942473
M3 - Conference contribution
AN - SCOPUS:85023179949
T3 - 2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017
BT - 2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017
Y2 - 24 April 2017 through 27 April 2017
ER -