Design and optimization methodology for 3D RRAM arrays

Yexin Deng, Hong Yu Chen, Bin Gao, Shimeng Yu, Shih Chieh Wu, Liang Zhao, Bing Chen, Zizhen Jiang, Xiaoyan Liu, Tuo Hung Hou, Yoshio Nishi, Jinfeng Kang, H. S Philip Wong

Research output: Chapter in Book/Report/Conference proceedingConference contribution

14 Citations (Scopus)

Abstract

3D RRAM arrays are studied at the device- and architecture-levels. The memory cell performance for a horizontal cross-point is shown experimentally to be essentially comparable to vertical pillar-around geometry. Array performances (read/write, energy, and speed) of different 3D architectures are investigated by SPICE simulation, showing horizontal stacked RRAM is superior but suffers from higher bit cost. Adopting a bi-layer pillar electrode structure is demonstrated to enlarge the array size in 3D vertical RRAM. Design guidelines are proposed for the 3D VRRAM: it shows that increasing the number of stacks of VRRAM while keeping the total bits the same, as well as scaling of feature size (F), are critical for reducing RC delay and energy consumption.

Original languageEnglish (US)
Title of host publicationTechnical Digest - International Electron Devices Meeting, IEDM
DOIs
StatePublished - 2013
Externally publishedYes
Event2013 IEEE International Electron Devices Meeting, IEDM 2013 - Washington, DC, United States
Duration: Dec 9 2013Dec 11 2013

Other

Other2013 IEEE International Electron Devices Meeting, IEDM 2013
CountryUnited States
CityWashington, DC
Period12/9/1312/11/13

Fingerprint

methodology
optimization
energy consumption
SPICE
Energy utilization
costs
scaling
Data storage equipment
Electrodes
electrodes
Geometry
geometry
cells
RRAM
Costs
simulation
energy

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Condensed Matter Physics
  • Electronic, Optical and Magnetic Materials
  • Materials Chemistry

Cite this

Deng, Y., Chen, H. Y., Gao, B., Yu, S., Wu, S. C., Zhao, L., ... Wong, H. S. P. (2013). Design and optimization methodology for 3D RRAM arrays. In Technical Digest - International Electron Devices Meeting, IEDM [6724693] https://doi.org/10.1109/IEDM.2013.6724693

Design and optimization methodology for 3D RRAM arrays. / Deng, Yexin; Chen, Hong Yu; Gao, Bin; Yu, Shimeng; Wu, Shih Chieh; Zhao, Liang; Chen, Bing; Jiang, Zizhen; Liu, Xiaoyan; Hou, Tuo Hung; Nishi, Yoshio; Kang, Jinfeng; Wong, H. S Philip.

Technical Digest - International Electron Devices Meeting, IEDM. 2013. 6724693.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Deng, Y, Chen, HY, Gao, B, Yu, S, Wu, SC, Zhao, L, Chen, B, Jiang, Z, Liu, X, Hou, TH, Nishi, Y, Kang, J & Wong, HSP 2013, Design and optimization methodology for 3D RRAM arrays. in Technical Digest - International Electron Devices Meeting, IEDM., 6724693, 2013 IEEE International Electron Devices Meeting, IEDM 2013, Washington, DC, United States, 12/9/13. https://doi.org/10.1109/IEDM.2013.6724693
Deng Y, Chen HY, Gao B, Yu S, Wu SC, Zhao L et al. Design and optimization methodology for 3D RRAM arrays. In Technical Digest - International Electron Devices Meeting, IEDM. 2013. 6724693 https://doi.org/10.1109/IEDM.2013.6724693
Deng, Yexin ; Chen, Hong Yu ; Gao, Bin ; Yu, Shimeng ; Wu, Shih Chieh ; Zhao, Liang ; Chen, Bing ; Jiang, Zizhen ; Liu, Xiaoyan ; Hou, Tuo Hung ; Nishi, Yoshio ; Kang, Jinfeng ; Wong, H. S Philip. / Design and optimization methodology for 3D RRAM arrays. Technical Digest - International Electron Devices Meeting, IEDM. 2013.
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