Design and optimization methodology for 3D RRAM arrays

Yexin Deng, Hong Yu Chen, Bin Gao, Shimeng Yu, Shih Chieh Wu, Liang Zhao, Bing Chen, Zizhen Jiang, Xiaoyan Liu, Tuo Hung Hou, Yoshio Nishi, Jinfeng Kang, H. S.Philip Wong

Research output: Chapter in Book/Report/Conference proceedingConference contribution

33 Scopus citations

Abstract

3D RRAM arrays are studied at the device- and architecture-levels. The memory cell performance for a horizontal cross-point is shown experimentally to be essentially comparable to vertical pillar-around geometry. Array performances (read/write, energy, and speed) of different 3D architectures are investigated by SPICE simulation, showing horizontal stacked RRAM is superior but suffers from higher bit cost. Adopting a bi-layer pillar electrode structure is demonstrated to enlarge the array size in 3D vertical RRAM. Design guidelines are proposed for the 3D VRRAM: it shows that increasing the number of stacks of VRRAM while keeping the total bits the same, as well as scaling of feature size (F), are critical for reducing RC delay and energy consumption.

Original languageEnglish (US)
Title of host publication2013 IEEE International Electron Devices Meeting, IEDM 2013
Pages25.7.1-25.7.4
DOIs
StatePublished - 2013
Event2013 IEEE International Electron Devices Meeting, IEDM 2013 - Washington, DC, United States
Duration: Dec 9 2013Dec 11 2013

Publication series

NameTechnical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)0163-1918

Other

Other2013 IEEE International Electron Devices Meeting, IEDM 2013
Country/TerritoryUnited States
CityWashington, DC
Period12/9/1312/11/13

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Materials Chemistry
  • Electrical and Electronic Engineering

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