Design and management of VFI partitioned networks-on-chip

Umit Y. Ogras, Radu Marculescu

Research output: Chapter in Book/Report/Conference proceedingChapter

Abstract

The design of many core systems-on-chip (SoCs) has become increasingly challenging due to high levels of integration, excessive energy consumption, and clock distribution problems. To deal with these issues, this chapter considers network-on-chip (NoC) architectures partitioned into several voltage-frequency islands (VFIs) and propose a design methodology for runtime energy management. The proposed approach minimizes the energy consumption subject to performance constraints. Then, we present efficient techniques for on-the-fly workload monitoring and management to ensure that the system can cope with variability in the workload and various technology-related parameters. Finally, the results and functional correctness are validated using an FPGA prototype for an NoC with multiple VFIs.

Original languageEnglish (US)
Title of host publicationModeling, Analysis and Optimization of Network-on-Chip Communication Architectures
Pages135-154
Number of pages20
DOIs
StatePublished - Apr 11 2013
Externally publishedYes

Publication series

NameLecture Notes in Electrical Engineering
Volume184
ISSN (Print)1876-1100
ISSN (Electronic)1876-1119

ASJC Scopus subject areas

  • Industrial and Manufacturing Engineering

Fingerprint Dive into the research topics of 'Design and management of VFI partitioned networks-on-chip'. Together they form a unique fingerprint.

  • Cite this

    Ogras, U. Y., & Marculescu, R. (2013). Design and management of VFI partitioned networks-on-chip. In Modeling, Analysis and Optimization of Network-on-Chip Communication Architectures (pp. 135-154). (Lecture Notes in Electrical Engineering; Vol. 184). https://doi.org/10.1007/978-94-007-3958-1-8