TY - GEN
T1 - Design and implementation of turbo decoders for software defined radio
AU - Lin, Yuan
AU - Mahlke, Scott
AU - Mudge, Trevor
AU - Chakrabarti, Chaitali
AU - Reid, Alastair
AU - Flautner, Krisztián
PY - 2006
Y1 - 2006
N2 - Software Defined Radio(SDR) is an emerging paradigm for wireless terminals, in which the physical layer of communication protocols is implemented in software rather than by ASICs. Many of the current and next generation wireless protocols include Turbo coding because of its superior performance. However, Turbo decoding is computationally intensive, and its low power implementations have typically been in ASICs. This paper presents a case study of algorithm-architecture co-design of Turbo decoder for SDR. We present a programmable DSP architecture for SDR that includes a set of architectural features to accelerate Turbo decoder computations. We then present a parallel window scheduling for MAX-Log-MAP component decoder that matches well with the DSP architecture. Finally, we present a software implementation of Turbo decoder for W-CDMA on the DSP architecture and show that it achieves 2Mbps decoding throughput.
AB - Software Defined Radio(SDR) is an emerging paradigm for wireless terminals, in which the physical layer of communication protocols is implemented in software rather than by ASICs. Many of the current and next generation wireless protocols include Turbo coding because of its superior performance. However, Turbo decoding is computationally intensive, and its low power implementations have typically been in ASICs. This paper presents a case study of algorithm-architecture co-design of Turbo decoder for SDR. We present a programmable DSP architecture for SDR that includes a set of architectural features to accelerate Turbo decoder computations. We then present a parallel window scheduling for MAX-Log-MAP component decoder that matches well with the DSP architecture. Finally, we present a software implementation of Turbo decoder for W-CDMA on the DSP architecture and show that it achieves 2Mbps decoding throughput.
UR - http://www.scopus.com/inward/record.url?scp=46249123815&partnerID=8YFLogxK
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U2 - 10.1109/SIPS.2006.352549
DO - 10.1109/SIPS.2006.352549
M3 - Conference contribution
AN - SCOPUS:46249123815
SN - 1424403820
SN - 9781424403820
T3 - 2006 IEEE Workshop on Signal Processing Systems Design and Implementation, SIPS
SP - 22
EP - 27
BT - 2006 IEEE Workshop on Signal Processing Systems Design and Implementation, SIPS
PB - IEEE Computer Society
T2 - IEEE Workshop on Signal Processing Systems, SIPS 2006
Y2 - 2 October 2006 through 4 October 2006
ER -