TY - JOUR
T1 - Design and evaluation of a spintronic in-memory processing platform for nonvolatile data encryption
AU - Angizi, Shaahin
AU - He, Zhezhi
AU - Bagherzadeh, Nader
AU - Fan, Deliang
N1 - Funding Information:
Manuscript received June 9, 2017; revised September 30, 2017; accepted November 12, 2017. Date of publication November 16, 2017; date of current version August 20, 2018. This work was supported in part by the National Science Foundation under Grant 1740126. This paper was recommended by Associate Editor Y. Chen. (Corresponding author: Shaahin Angizi.) S. Angizi, Z. He, and D. Fan are with the Department of Electrical and Computer Engineering, University of Central Florida, Orlando, FL 32816 USA (e-mail: angizi@knights.ucf.edu; elliot.he@knights.ucf.edu; dfan@ucf.edu).
Publisher Copyright:
© 1982-2012 IEEE.
PY - 2018/9
Y1 - 2018/9
N2 - In this paper, we propose an energy-efficient reconfigurable platform for in-memory processing based on novel four-terminal spin Hall effect-driven domain wall motion devices that could be employed as both nonvolatile memory cell and in-memory logic unit. The proposed designs lead to unity of memory and logic. The device to system level simulation results show that, with 28% area increase in memory structure, the proposed in-memory processing platform achieves a write energy 15.6 fJ/bit with 79% reduction compared to that of SOT-MRAM counterpart while keeping the identical 1 ns writing speed. In addition, the proposed in-memory logic scheme improves the operating energy by 61.3%, as compared with the recent nonvolatile in-memory logic designs. An extensive reliability analysis is also performed over the proposed circuits. We employ advanced encryption standard (AES) algorithm as a case study to elucidate the efficiency of the proposed platform at application level. Simulation results exhibit that the proposed platform can show up to 75.7% and 30.4% lower energy consumption compared to CMOS-ASIC and recent pipelined domain wall (DW) AES implementations, respectively. In addition, the AES energy-delay product can show 15.1% and 6.1% improvements compared to the DW-AES and CMOS-ASIC implementations, respectively.
AB - In this paper, we propose an energy-efficient reconfigurable platform for in-memory processing based on novel four-terminal spin Hall effect-driven domain wall motion devices that could be employed as both nonvolatile memory cell and in-memory logic unit. The proposed designs lead to unity of memory and logic. The device to system level simulation results show that, with 28% area increase in memory structure, the proposed in-memory processing platform achieves a write energy 15.6 fJ/bit with 79% reduction compared to that of SOT-MRAM counterpart while keeping the identical 1 ns writing speed. In addition, the proposed in-memory logic scheme improves the operating energy by 61.3%, as compared with the recent nonvolatile in-memory logic designs. An extensive reliability analysis is also performed over the proposed circuits. We employ advanced encryption standard (AES) algorithm as a case study to elucidate the efficiency of the proposed platform at application level. Simulation results exhibit that the proposed platform can show up to 75.7% and 30.4% lower energy consumption compared to CMOS-ASIC and recent pipelined domain wall (DW) AES implementations, respectively. In addition, the AES energy-delay product can show 15.1% and 6.1% improvements compared to the DW-AES and CMOS-ASIC implementations, respectively.
KW - Advanced encryption standard (AES)
KW - domain wall motion (DWM)
KW - in-memory processing platform
KW - spin Hall effect (SHE)
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U2 - 10.1109/TCAD.2017.2774291
DO - 10.1109/TCAD.2017.2774291
M3 - Article
AN - SCOPUS:85035086354
SN - 0278-0070
VL - 37
SP - 1788
EP - 1801
JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IS - 9
M1 - 8113549
ER -