Design and analysis of LDPC decoders for software defined radio

Sangwon Seo, Trevor Mudge, Yuming Zhu, Chaitali Chakrabarti

Research output: Chapter in Book/Report/Conference proceedingConference contribution

26 Scopus citations

Abstract

Low Density Parity Check (LDPC) codes are one of the most promising error correction codes that are being adopted by many wireless standards. This paper presents a case study for a scalable LDPC decoder supporting multiple code rates and multiple block sizes on a software defined radio (SDR) platform. Since technology scaling alone is not sufficient for current SDR architectures to meet the requirements of the next generation wireless standards, this paper presents three techniques to improve the throughput performance. The techniques are use of data path accelerators, addition of memory units and addition of a few assembly instructions. The proposed LDPC decoder implementation achieved 30.4 Mbps decoding throughput for the n=2304 and R=5/6 LDPC code outlined in the IEEE 802.16e standard.

Original languageEnglish (US)
Title of host publication2007 IEEE Workshop on Signal Processing Systems, SiPS 2007, Proceedings
Pages210-215
Number of pages6
DOIs
StatePublished - Dec 1 2007
Event2007 IEEE Workshop on Signal Processing Systems, SiPS 2007 - Shanghai, China
Duration: Oct 17 2007Oct 19 2007

Publication series

NameIEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
ISSN (Print)1520-6130

Other

Other2007 IEEE Workshop on Signal Processing Systems, SiPS 2007
Country/TerritoryChina
CityShanghai
Period10/17/0710/19/07

Keywords

  • LDPC
  • Min-sum iterative decoding
  • SDR
  • SIMD
  • SODA

ASJC Scopus subject areas

  • Media Technology
  • Signal Processing

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