Design and analysis of a CMOS passive ∑δ ADC for low power RF transceivers

Feng Chen, Bertan Bakkaloglu, Srinath Ramaswamy

Research output: Contribution to journalArticlepeer-review

16 Scopus citations

Abstract

Design and analysis of a ∑?δ modulator with a passive switched capacitor loop filter is presented. Design steps for optimum loop filter design for quantization noise suppression and thermal noise reduction is outlined. Design specifications for sampling clock phase noise, reference buffer and input buffer settling is analyzed. Presented design has a 2nd-order loop filter and uses only metal-metal capacitors and thin oxide digital transistors with no additional components occupying less than 0.1 mm2 silicon area in 0.13 μm CMOS digital process. Measurement results show that the ADC achieves 80 dB peak SNR at a 100 kHz integration bandwidth with 1 pJ/sample conversion efficiency. With decimation filter power consumption of 0.22 mW at 104 MHz sampling rate, the ADC consumes only about 1 mA at 1.5 V for each channel.

Original languageEnglish (US)
Pages (from-to)129-141
Number of pages13
JournalAnalog Integrated Circuits and Signal Processing
Volume59
Issue number2
DOIs
StatePublished - May 1 2009

Keywords

  • Clock phase noise
  • RF transceivers
  • Sigma-delta analog to digital converters

ASJC Scopus subject areas

  • Signal Processing
  • Hardware and Architecture
  • Surfaces, Coatings and Films

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