DELAY TIME AND SIGNAL PROPAGATION IN LARGE-SCALE INTEGRATED CIRCUITS.

R. O. Grondin, W. Porod, D. K. Ferry

Research output: Contribution to journalArticle

6 Citations (Scopus)

Abstract

Power dissipation and signal propagation are considered for the logic circuits in future VLSI. When these are coupled to the necessity to dissipate power and to fundamental limits on the energy dissipation, a constraint which is almost geometry independent is obtained. At one extreme, the fundamental limits suggest a minimum delay time of 0. 01 ps. At the opposite extreme, values appropriate to conventional technology lead to a delay time per gate that is constrained to have a lower limit of about 0. 2 ns in the wire-dominated chip.

Original languageEnglish (US)
Pages (from-to)262-263
Number of pages2
JournalIEEE Journal of Solid-State Circuits
VolumeSC-19
Issue number2
StatePublished - Apr 1984
Externally publishedYes

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Integrated circuits
Time delay
Energy dissipation
Logic circuits
Wire
Geometry

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Grondin, R. O., Porod, W., & Ferry, D. K. (1984). DELAY TIME AND SIGNAL PROPAGATION IN LARGE-SCALE INTEGRATED CIRCUITS. IEEE Journal of Solid-State Circuits, SC-19(2), 262-263.

DELAY TIME AND SIGNAL PROPAGATION IN LARGE-SCALE INTEGRATED CIRCUITS. / Grondin, R. O.; Porod, W.; Ferry, D. K.

In: IEEE Journal of Solid-State Circuits, Vol. SC-19, No. 2, 04.1984, p. 262-263.

Research output: Contribution to journalArticle

Grondin, RO, Porod, W & Ferry, DK 1984, 'DELAY TIME AND SIGNAL PROPAGATION IN LARGE-SCALE INTEGRATED CIRCUITS.', IEEE Journal of Solid-State Circuits, vol. SC-19, no. 2, pp. 262-263.
Grondin, R. O. ; Porod, W. ; Ferry, D. K. / DELAY TIME AND SIGNAL PROPAGATION IN LARGE-SCALE INTEGRATED CIRCUITS. In: IEEE Journal of Solid-State Circuits. 1984 ; Vol. SC-19, No. 2. pp. 262-263.
@article{24b72fe2ad3842c9895603a4ec0210b1,
title = "DELAY TIME AND SIGNAL PROPAGATION IN LARGE-SCALE INTEGRATED CIRCUITS.",
abstract = "Power dissipation and signal propagation are considered for the logic circuits in future VLSI. When these are coupled to the necessity to dissipate power and to fundamental limits on the energy dissipation, a constraint which is almost geometry independent is obtained. At one extreme, the fundamental limits suggest a minimum delay time of 0. 01 ps. At the opposite extreme, values appropriate to conventional technology lead to a delay time per gate that is constrained to have a lower limit of about 0. 2 ns in the wire-dominated chip.",
author = "Grondin, {R. O.} and W. Porod and Ferry, {D. K.}",
year = "1984",
month = "4",
language = "English (US)",
volume = "SC-19",
pages = "262--263",
journal = "IEEE Journal of Solid-State Circuits",
issn = "0018-9200",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "2",

}

TY - JOUR

T1 - DELAY TIME AND SIGNAL PROPAGATION IN LARGE-SCALE INTEGRATED CIRCUITS.

AU - Grondin, R. O.

AU - Porod, W.

AU - Ferry, D. K.

PY - 1984/4

Y1 - 1984/4

N2 - Power dissipation and signal propagation are considered for the logic circuits in future VLSI. When these are coupled to the necessity to dissipate power and to fundamental limits on the energy dissipation, a constraint which is almost geometry independent is obtained. At one extreme, the fundamental limits suggest a minimum delay time of 0. 01 ps. At the opposite extreme, values appropriate to conventional technology lead to a delay time per gate that is constrained to have a lower limit of about 0. 2 ns in the wire-dominated chip.

AB - Power dissipation and signal propagation are considered for the logic circuits in future VLSI. When these are coupled to the necessity to dissipate power and to fundamental limits on the energy dissipation, a constraint which is almost geometry independent is obtained. At one extreme, the fundamental limits suggest a minimum delay time of 0. 01 ps. At the opposite extreme, values appropriate to conventional technology lead to a delay time per gate that is constrained to have a lower limit of about 0. 2 ns in the wire-dominated chip.

UR - http://www.scopus.com/inward/record.url?scp=0021406450&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0021406450&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:0021406450

VL - SC-19

SP - 262

EP - 263

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

SN - 0018-9200

IS - 2

ER -