Delay Time and Signal Propagation in Large-Scale Integrated Circuits

R. O. Grondin, W. Porod, D. K. Ferry

Research output: Contribution to journalArticle

6 Scopus citations

Abstract

Power dissipation and signal propagation are considered for the logic circuits in future VLSI. When these are coupled to the necessity to dissipate power and to fundamental limits on the energy dissipation, a constraint which is almost geometry independent is obtained. At one extreme, the fundamental limits suggest a minimum delay time of 0.01 ps. At the opposite extreme, values appropriate to conventional technology lead to a delay time per gate that is constrained to have a lower limit of about 0.2 ns in the wire-dominated chip.

Original languageEnglish (US)
Pages (from-to)262-263
Number of pages2
JournalIEEE Journal of Solid-State Circuits
Volume19
Issue number2
DOIs
StatePublished - Apr 1984

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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