@inproceedings{6deecbb4d3044a78bbc24ef04b98a419,
title = "Delay and power tradeoffs for static and dynamic register files",
abstract = "Register file (RF) memory is important in low power SOCs due to its inherent low voltage stability. Moreover, designs increasingly use compiled instead of custom memory blocks, which frequently employ static, rather than pre-charged dynamic register files. In this paper, we compare static and dynamic RF power dissipation and timing characteristics. The relative timing and power advantages of the designs are shown to be dependent on the memory aspect ratio, i.e. array width and height. One version, fabricated on a foundry bulk CMOS 90-nm low standby power (LP) process provides a baseline for the analyses.",
keywords = "8-T SRAM, Register file, cache, dynamic circuits",
author = "Vinay Vashishtha and Aditya Gujja and Clark, {Lawrence T.}",
note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; IEEE International Symposium on Circuits and Systems, ISCAS 2015 ; Conference date: 24-05-2015 Through 27-05-2015",
year = "2015",
month = jul,
day = "27",
doi = "10.1109/ISCAS.2015.7169293",
language = "English (US)",
series = "Proceedings - IEEE International Symposium on Circuits and Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "2900--2903",
booktitle = "2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015",
}