Delay and power tradeoffs for static and dynamic register files

Vinay Vashishtha, Aditya Gujja, Lawrence T. Clark

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

Register file (RF) memory is important in low power SOCs due to its inherent low voltage stability. Moreover, designs increasingly use compiled instead of custom memory blocks, which frequently employ static, rather than pre-charged dynamic register files. In this paper, we compare static and dynamic RF power dissipation and timing characteristics. The relative timing and power advantages of the designs are shown to be dependent on the memory aspect ratio, i.e. array width and height. One version, fabricated on a foundry bulk CMOS 90-nm low standby power (LP) process provides a baseline for the analyses.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages2900-2903
Number of pages4
Volume2015-July
ISBN (Print)9781479983919
DOIs
StatePublished - Jul 27 2015
EventIEEE International Symposium on Circuits and Systems, ISCAS 2015 - Lisbon, Portugal
Duration: May 24 2015May 27 2015

Other

OtherIEEE International Symposium on Circuits and Systems, ISCAS 2015
CountryPortugal
CityLisbon
Period5/24/155/27/15

Keywords

  • 8-T SRAM
  • cache
  • dynamic circuits
  • Register file

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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    Vashishtha, V., Gujja, A., & Clark, L. T. (2015). Delay and power tradeoffs for static and dynamic register files. In Proceedings - IEEE International Symposium on Circuits and Systems (Vol. 2015-July, pp. 2900-2903). [7169293] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2015.7169293