Delay and power tradeoffs for static and dynamic register files

Vinay Vashishtha; Aditya Gujja; Lawrence T. Clark

doi:10.1109/ISCAS.2015.7169293

Delay and power tradeoffs for static and dynamic register files

Vinay Vashishtha, Aditya Gujja, Lawrence T. Clark

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Scopus citations

Abstract

Register file (RF) memory is important in low power SOCs due to its inherent low voltage stability. Moreover, designs increasingly use compiled instead of custom memory blocks, which frequently employ static, rather than pre-charged dynamic register files. In this paper, we compare static and dynamic RF power dissipation and timing characteristics. The relative timing and power advantages of the designs are shown to be dependent on the memory aspect ratio, i.e. array width and height. One version, fabricated on a foundry bulk CMOS 90-nm low standby power (LP) process provides a baseline for the analyses.

Original language	English (US)
Title of host publication	Proceedings - IEEE International Symposium on Circuits and Systems
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	2900-2903
Number of pages	4
Volume	2015-July
ISBN (Print)	9781479983919
DOIs	https://doi.org/10.1109/ISCAS.2015.7169293
State	Published - Jul 27 2015
Event	IEEE International Symposium on Circuits and Systems, ISCAS 2015 - Lisbon, Portugal Duration: May 24 2015 → May 27 2015

Other

Other	IEEE International Symposium on Circuits and Systems, ISCAS 2015
Country/Territory	Portugal
City	Lisbon
Period	5/24/15 → 5/27/15

Keywords

8-T SRAM
cache
dynamic circuits
Register file

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/ISCAS.2015.7169293

Cite this

Delay and power tradeoffs for static and dynamic register files. / Vashishtha, Vinay; Gujja, Aditya; Clark, Lawrence T.

Proceedings - IEEE International Symposium on Circuits and Systems. Vol. 2015-July Institute of Electrical and Electronics Engineers Inc., 2015. p. 2900-2903 7169293.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Vashishtha, V, Gujja, A & Clark, LT 2015, Delay and power tradeoffs for static and dynamic register files. in Proceedings - IEEE International Symposium on Circuits and Systems. vol. 2015-July, 7169293, Institute of Electrical and Electronics Engineers Inc., pp. 2900-2903, IEEE International Symposium on Circuits and Systems, ISCAS 2015, Lisbon, Portugal, 5/24/15. https://doi.org/10.1109/ISCAS.2015.7169293

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abstract = "Register file (RF) memory is important in low power SOCs due to its inherent low voltage stability. Moreover, designs increasingly use compiled instead of custom memory blocks, which frequently employ static, rather than pre-charged dynamic register files. In this paper, we compare static and dynamic RF power dissipation and timing characteristics. The relative timing and power advantages of the designs are shown to be dependent on the memory aspect ratio, i.e. array width and height. One version, fabricated on a foundry bulk CMOS 90-nm low standby power (LP) process provides a baseline for the analyses.",

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AU - Vashishtha, Vinay

AU - Gujja, Aditya

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N2 - Register file (RF) memory is important in low power SOCs due to its inherent low voltage stability. Moreover, designs increasingly use compiled instead of custom memory blocks, which frequently employ static, rather than pre-charged dynamic register files. In this paper, we compare static and dynamic RF power dissipation and timing characteristics. The relative timing and power advantages of the designs are shown to be dependent on the memory aspect ratio, i.e. array width and height. One version, fabricated on a foundry bulk CMOS 90-nm low standby power (LP) process provides a baseline for the analyses.

AB - Register file (RF) memory is important in low power SOCs due to its inherent low voltage stability. Moreover, designs increasingly use compiled instead of custom memory blocks, which frequently employ static, rather than pre-charged dynamic register files. In this paper, we compare static and dynamic RF power dissipation and timing characteristics. The relative timing and power advantages of the designs are shown to be dependent on the memory aspect ratio, i.e. array width and height. One version, fabricated on a foundry bulk CMOS 90-nm low standby power (LP) process provides a baseline for the analyses.

KW - 8-T SRAM

KW - cache

KW - dynamic circuits

KW - Register file

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BT - Proceedings - IEEE International Symposium on Circuits and Systems

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ER -

Delay and power tradeoffs for static and dynamic register files

Abstract

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Keywords

ASJC Scopus subject areas

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