Abstract
Register file (RF) memory is important in low power SOCs due to its inherent low voltage stability. Moreover, designs increasingly use compiled instead of custom memory blocks, which frequently employ static, rather than pre-charged dynamic register files. In this paper, we compare static and dynamic RF power dissipation and timing characteristics. The relative timing and power advantages of the designs are shown to be dependent on the memory aspect ratio, i.e. array width and height. One version, fabricated on a foundry bulk CMOS 90-nm low standby power (LP) process provides a baseline for the analyses.
Original language | English (US) |
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Title of host publication | Proceedings - IEEE International Symposium on Circuits and Systems |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 2900-2903 |
Number of pages | 4 |
Volume | 2015-July |
ISBN (Print) | 9781479983919 |
DOIs | |
State | Published - Jul 27 2015 |
Event | IEEE International Symposium on Circuits and Systems, ISCAS 2015 - Lisbon, Portugal Duration: May 24 2015 → May 27 2015 |
Other
Other | IEEE International Symposium on Circuits and Systems, ISCAS 2015 |
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Country | Portugal |
City | Lisbon |
Period | 5/24/15 → 5/27/15 |
Keywords
- 8-T SRAM
- cache
- dynamic circuits
- Register file
ASJC Scopus subject areas
- Electrical and Electronic Engineering