Delay and power tradeoffs for static and dynamic register files

Vinay Vashishtha; Aditya Gujja; Lawrence T. Clark

doi:10.1109/ISCAS.2015.7169293

Delay and power tradeoffs for static and dynamic register files

Vinay Vashishtha, Aditya Gujja, Lawrence T. Clark

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Scopus citations

Abstract

Register file (RF) memory is important in low power SOCs due to its inherent low voltage stability. Moreover, designs increasingly use compiled instead of custom memory blocks, which frequently employ static, rather than pre-charged dynamic register files. In this paper, we compare static and dynamic RF power dissipation and timing characteristics. The relative timing and power advantages of the designs are shown to be dependent on the memory aspect ratio, i.e. array width and height. One version, fabricated on a foundry bulk CMOS 90-nm low standby power (LP) process provides a baseline for the analyses.

Original language	English (US)
Title of host publication	2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	2900-2903
Number of pages	4
ISBN (Electronic)	9781479983919
DOIs	https://doi.org/10.1109/ISCAS.2015.7169293
State	Published - Jul 27 2015
Event	IEEE International Symposium on Circuits and Systems, ISCAS 2015 - Lisbon, Portugal Duration: May 24 2015 → May 27 2015

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2015-July
ISSN (Print)	0271-4310

Other

Other	IEEE International Symposium on Circuits and Systems, ISCAS 2015
Country/Territory	Portugal
City	Lisbon
Period	5/24/15 → 5/27/15

Keywords

8-T SRAM
Register file
cache
dynamic circuits

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/ISCAS.2015.7169293

Cite this

Vashishtha, V., Gujja, A., & Clark, L. T. (2015). Delay and power tradeoffs for static and dynamic register files. In 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015 (pp. 2900-2903). [7169293] (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2015-July). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2015.7169293

Delay and power tradeoffs for static and dynamic register files. / Vashishtha, Vinay; Gujja, Aditya; Clark, Lawrence T.

2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 2900-2903 7169293 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2015-July).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Vashishtha, V, Gujja, A & Clark, LT 2015, Delay and power tradeoffs for static and dynamic register files. in 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015., 7169293, Proceedings - IEEE International Symposium on Circuits and Systems, vol. 2015-July, Institute of Electrical and Electronics Engineers Inc., pp. 2900-2903, IEEE International Symposium on Circuits and Systems, ISCAS 2015, Lisbon, Portugal, 5/24/15. https://doi.org/10.1109/ISCAS.2015.7169293

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abstract = "Register file (RF) memory is important in low power SOCs due to its inherent low voltage stability. Moreover, designs increasingly use compiled instead of custom memory blocks, which frequently employ static, rather than pre-charged dynamic register files. In this paper, we compare static and dynamic RF power dissipation and timing characteristics. The relative timing and power advantages of the designs are shown to be dependent on the memory aspect ratio, i.e. array width and height. One version, fabricated on a foundry bulk CMOS 90-nm low standby power (LP) process provides a baseline for the analyses.",

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ER -

Delay and power tradeoffs for static and dynamic register files

Abstract

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Keywords

ASJC Scopus subject areas

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