Delay and area efficient first-level cache soft error detection and correction

Karl C. Mohr, Lawrence T. Clark

Research output: Chapter in Book/Report/Conference proceedingConference contribution

26 Scopus citations

Abstract

Soft error rates are an increasing problem in modern VLSI circuits. Commonly used error correcting codes reduce soft error rates in large memories and second level caches but are not suited to small fast memories such as first level caches, due to the area and speed penalties they entail. Here, an error detection and correction scheme that is appropriate for use in low latency first level caches and other small, fast memories such as register files is presented. The scheme allows fine, e.g., byte write granularity with acceptable storage overhead. Analysis demonstrates that the proposed method provides adequate soft error rate reduction with improved latency and area cost.

Original languageEnglish (US)
Title of host publicationIEEE International Conference on Computer Design, ICCD 2006
Pages88-92
Number of pages5
DOIs
Publication statusPublished - 2006
Event24th International Conference on Computer Design 2006, ICCD - San Jose, CA, United States
Duration: Oct 1 2006Oct 4 2006

Other

Other24th International Conference on Computer Design 2006, ICCD
CountryUnited States
CitySan Jose, CA
Period10/1/0610/4/06

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Keywords

  • Error correcting codes
  • Error detection and correction
  • Memory soft errors

ASJC Scopus subject areas

  • Computer Graphics and Computer-Aided Design
  • Software

Cite this

Mohr, K. C., & Clark, L. T. (2006). Delay and area efficient first-level cache soft error detection and correction. In IEEE International Conference on Computer Design, ICCD 2006 (pp. 88-92). [4380799] https://doi.org/10.1109/ICCD.2006.4380799