Delay and area efficient first-level cache soft error detection and correction

Karl C. Mohr; Lawrence T. Clark

doi:10.1109/ICCD.2006.4380799

Delay and area efficient first-level cache soft error detection and correction

Karl C. Mohr, Lawrence T. Clark

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

32 Scopus citations

Abstract

Soft error rates are an increasing problem in modern VLSI circuits. Commonly used error correcting codes reduce soft error rates in large memories and second level caches but are not suited to small fast memories such as first level caches, due to the area and speed penalties they entail. Here, an error detection and correction scheme that is appropriate for use in low latency first level caches and other small, fast memories such as register files is presented. The scheme allows fine, e.g., byte write granularity with acceptable storage overhead. Analysis demonstrates that the proposed method provides adequate soft error rate reduction with improved latency and area cost.

Original language	English (US)
Title of host publication	IEEE International Conference on Computer Design, ICCD 2006
Pages	88-92
Number of pages	5
DOIs	https://doi.org/10.1109/ICCD.2006.4380799
State	Published - 2006
Event	24th International Conference on Computer Design 2006, ICCD - San Jose, CA, United States Duration: Oct 1 2006 → Oct 4 2006

Other

Other	24th International Conference on Computer Design 2006, ICCD
Country/Territory	United States
City	San Jose, CA
Period	10/1/06 → 10/4/06

Keywords

Error correcting codes
Error detection and correction
Memory soft errors

ASJC Scopus subject areas

Computer Graphics and Computer-Aided Design
Software

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10.1109/ICCD.2006.4380799

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@inproceedings{b8e3384b02394d2fbb60841da9f2c1d6,

title = "Delay and area efficient first-level cache soft error detection and correction",

abstract = "Soft error rates are an increasing problem in modern VLSI circuits. Commonly used error correcting codes reduce soft error rates in large memories and second level caches but are not suited to small fast memories such as first level caches, due to the area and speed penalties they entail. Here, an error detection and correction scheme that is appropriate for use in low latency first level caches and other small, fast memories such as register files is presented. The scheme allows fine, e.g., byte write granularity with acceptable storage overhead. Analysis demonstrates that the proposed method provides adequate soft error rate reduction with improved latency and area cost.",

keywords = "Error correcting codes, Error detection and correction, Memory soft errors",

author = "Mohr, {Karl C.} and Clark, {Lawrence T.}",

year = "2006",

doi = "10.1109/ICCD.2006.4380799",

language = "English (US)",

pages = "88--92",

booktitle = "IEEE International Conference on Computer Design, ICCD 2006",

note = "24th International Conference on Computer Design 2006, ICCD ; Conference date: 01-10-2006 Through 04-10-2006",

}

TY - GEN

T1 - Delay and area efficient first-level cache soft error detection and correction

AU - Mohr, Karl C.

AU - Clark, Lawrence T.

PY - 2006

Y1 - 2006

N2 - Soft error rates are an increasing problem in modern VLSI circuits. Commonly used error correcting codes reduce soft error rates in large memories and second level caches but are not suited to small fast memories such as first level caches, due to the area and speed penalties they entail. Here, an error detection and correction scheme that is appropriate for use in low latency first level caches and other small, fast memories such as register files is presented. The scheme allows fine, e.g., byte write granularity with acceptable storage overhead. Analysis demonstrates that the proposed method provides adequate soft error rate reduction with improved latency and area cost.

AB - Soft error rates are an increasing problem in modern VLSI circuits. Commonly used error correcting codes reduce soft error rates in large memories and second level caches but are not suited to small fast memories such as first level caches, due to the area and speed penalties they entail. Here, an error detection and correction scheme that is appropriate for use in low latency first level caches and other small, fast memories such as register files is presented. The scheme allows fine, e.g., byte write granularity with acceptable storage overhead. Analysis demonstrates that the proposed method provides adequate soft error rate reduction with improved latency and area cost.

KW - Error correcting codes

KW - Error detection and correction

KW - Memory soft errors

UR - http://www.scopus.com/inward/record.url?scp=47249154292&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=47249154292&partnerID=8YFLogxK

U2 - 10.1109/ICCD.2006.4380799

DO - 10.1109/ICCD.2006.4380799

M3 - Conference contribution

AN - SCOPUS:47249154292

SP - 88

EP - 92

BT - IEEE International Conference on Computer Design, ICCD 2006

T2 - 24th International Conference on Computer Design 2006, ICCD

Y2 - 1 October 2006 through 4 October 2006

ER -

Delay and area efficient first-level cache soft error detection and correction

Abstract

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Keywords

ASJC Scopus subject areas

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