Degradation effects in a-si:h thin film transistors and their impact on circuit performance

David Allee, Lawrence T. Clark, Rahul Shringarpure, Sameer M. Venugopal, Zi P. Li, Edward J. Bawolek

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Scopus citations

Abstract

Amorphous silicon thin film transistors degrade with electrical stress. In particular, the threshold voltage increases significantly with positive gate voltages. The characteristics and mechanisms of the degradation are reviewed. The implications for various types of circuitry including active matrix backplanes, integrated drivers and general purpose digital circuitry are examined. A circuit modeling tool that enables the prediction of complex circuit degradation is presented. Finally, the similarity of degradation in amorphous silicon to negative bias temperature instability in crystalline PMOS is discussed along with potential approaches to reducing the degradation effects.

Original languageEnglish (US)
Title of host publication46th Annual 2008 IEEE International Reliability Physics Symposium Proceedings, IRPS
Pages158-167
Number of pages10
DOIs
StatePublished - Sep 17 2008
Event46th Annual 2008 IEEE International Reliability Physics Symposium, IRPS - Phoenix, AZ, United States
Duration: Apr 27 2008May 1 2008

Publication series

NameIEEE International Reliability Physics Symposium Proceedings
ISSN (Print)1541-7026

Other

Other46th Annual 2008 IEEE International Reliability Physics Symposium, IRPS
CountryUnited States
CityPhoenix, AZ
Period4/27/085/1/08

ASJC Scopus subject areas

  • Engineering(all)

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