TY - GEN
T1 - Defect-based test optimization for analog/RF circuits for near-zero DPPM applications
AU - Yilmaz, Ender
AU - Ozev, Sule
PY - 2009
Y1 - 2009
N2 - Analog circuits are often tested based on their specifications. While specification-based testing ensures the initial product quality, full testing is often not possible in high volume production. Moreover, even full specification-based testing cannot guarantee that the circuit does not contain any physical defects. Some application domains require near-zero defect levels independent of whether the specifications are met. In this work, we present a defect based test optimization method focusing on defective parts per million (DPPM) minimization. We extract potential defects through inductive fault analysis (IFA) and reduce the number of tests without degrading the test quality. In order to achieve near zero DPPM, we employ outlier analysis to identify defective circuits that cannot be identified using specification based methods. Simulation results on an LNA show that DPPM is reduced down to 0 at a cost of 0.2% yield loss with the proposed method.
AB - Analog circuits are often tested based on their specifications. While specification-based testing ensures the initial product quality, full testing is often not possible in high volume production. Moreover, even full specification-based testing cannot guarantee that the circuit does not contain any physical defects. Some application domains require near-zero defect levels independent of whether the specifications are met. In this work, we present a defect based test optimization method focusing on defective parts per million (DPPM) minimization. We extract potential defects through inductive fault analysis (IFA) and reduce the number of tests without degrading the test quality. In order to achieve near zero DPPM, we employ outlier analysis to identify defective circuits that cannot be identified using specification based methods. Simulation results on an LNA show that DPPM is reduced down to 0 at a cost of 0.2% yield loss with the proposed method.
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U2 - 10.1109/ICCD.2009.5413139
DO - 10.1109/ICCD.2009.5413139
M3 - Conference contribution
AN - SCOPUS:77951015304
SN - 9781424450282
T3 - Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
SP - 313
EP - 318
BT - 2009 IEEE International Conference on Computer Design, ICCD 2009
T2 - 2009 IEEE International Conference on Computer Design, ICCD 2009
Y2 - 4 October 2009 through 7 October 2009
ER -