Defect-based compact model for circuit reliability simulation in advanced CMOS technologies

I. S. Esqueda, Hugh Barnaby

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Scopus citations

Abstract

A defect-based compact modeling approach for circuit reliability simulation based on surface potential calculations is presented. The modeling approach captures the bias-dependence of stress-induced defects such as (bulk) oxide-trapped charge and interface traps that cannot be described by typical fixed voltage shift models (i.e., threshold voltage, Vth-based models). The defect dynamic charge contribution is modeled under non-equilibrium conditions and for all regions of operation (i.e. from weak to strong inversion) and not just at the threshold (as in Vth-based models). The modeled is verified with 2-D TCAD simulations that incorporate oxide trapped charge and interface trap densities. Spice-level simulations of ring oscillators and SRAM cells reveal inaccuracies in describing aging effects when utilizing typical fixed voltage shift models as compared to the presented defect-based compact modeling approach.

Original languageEnglish (US)
Title of host publication2013 IEEE International Integrated Reliability Workshop Final Report, IIRW 2013
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages45-49
Number of pages5
ISBN (Print)9781479903504
DOIs
StatePublished - Jan 1 2013
Event2013 IEEE International Integrated Reliability Workshop Final Report, IIRW 2013 - South Lake Tahoe, CA, United States
Duration: Oct 13 2013Oct 17 2013

Publication series

NameIEEE International Integrated Reliability Workshop Final Report

Other

Other2013 IEEE International Integrated Reliability Workshop Final Report, IIRW 2013
CountryUnited States
CitySouth Lake Tahoe, CA
Period10/13/1310/17/13

    Fingerprint

Keywords

  • CMOS
  • Interface traps
  • NBTI
  • SRAM
  • aging
  • circuit simulation
  • reliability
  • ring oscillator
  • stress
  • surface potential

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality
  • Electronic, Optical and Magnetic Materials

Cite this

Esqueda, I. S., & Barnaby, H. (2013). Defect-based compact model for circuit reliability simulation in advanced CMOS technologies. In 2013 IEEE International Integrated Reliability Workshop Final Report, IIRW 2013 (pp. 45-49). [6804155] (IEEE International Integrated Reliability Workshop Final Report). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IIRW.2013.6804155