@inproceedings{7c4710a8ac484107920843b2a986cb36,
title = "Defect-based compact model for circuit reliability simulation in advanced CMOS technologies",
abstract = "A defect-based compact modeling approach for circuit reliability simulation based on surface potential calculations is presented. The modeling approach captures the bias-dependence of stress-induced defects such as (bulk) oxide-trapped charge and interface traps that cannot be described by typical fixed voltage shift models (i.e., threshold voltage, Vth-based models). The defect dynamic charge contribution is modeled under non-equilibrium conditions and for all regions of operation (i.e. from weak to strong inversion) and not just at the threshold (as in Vth-based models). The modeled is verified with 2-D TCAD simulations that incorporate oxide trapped charge and interface trap densities. Spice-level simulations of ring oscillators and SRAM cells reveal inaccuracies in describing aging effects when utilizing typical fixed voltage shift models as compared to the presented defect-based compact modeling approach.",
keywords = "CMOS, Interface traps, NBTI, SRAM, aging, circuit simulation, reliability, ring oscillator, stress, surface potential",
author = "Esqueda, {I. S.} and Hugh Barnaby",
year = "2013",
doi = "10.1109/IIRW.2013.6804155",
language = "English (US)",
isbn = "9781479903504",
series = "IEEE International Integrated Reliability Workshop Final Report",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "45--49",
booktitle = "2013 IEEE International Integrated Reliability Workshop Final Report, IIRW 2013",
note = "2013 IEEE International Integrated Reliability Workshop Final Report, IIRW 2013 ; Conference date: 13-10-2013 Through 17-10-2013",
}