Deep Convolutional Neural Network Accelerator Featuring Conditional Computing and Low External Memory Access

Minkyu Kim, Jae Sun Seo

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents an ASIC accelerator for deep convolutional neural networks (DCNNs) featuring a novel conditional computing scheme that synergistically combines precision-cascading with zero-skipping. To reduce many redundant convolution operations that are followed by max-pooling operations, we propose precision-cascading, where the input features are divided into a number of low-precision groups and approximate convolutions with only the most significant bits (MSBs) are performed first. Based on this approximate computation, the full-precision convolution is performed only on the maximum pooling output that is found. This way, the total number of bit-wise convolutions can be reduced by 2× without affecting the output feature values and with <0.8% degradation in final ImageNet classification accuracy. Precision-cascading provides the added benefit of increased sparsity per low-precision group, which we exploit with zero-skipping to eliminate clock cycles as well as external memory access that involve zero inputs. By jointly optimizing the conditional computing scheme and hardware architecture, the 40nm prototype chip demonstrates a peak energy-efficiency of 8.85 TOPS/W at 0.9V supply and low external memory access of 55.31 MB (or 0.0018 access/MAC) for ImageNet classification with VGG-16 CNN.

Original languageEnglish (US)
Title of host publication2020 IEEE Custom Integrated Circuits Conference, CICC 2020
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728160313
DOIs
StatePublished - Mar 2020
Event2020 IEEE Custom Integrated Circuits Conference, CICC 2020 - Boston, United States
Duration: Mar 22 2020Mar 25 2020

Publication series

NameProceedings of the Custom Integrated Circuits Conference
Volume2020-March
ISSN (Print)0886-5930

Conference

Conference2020 IEEE Custom Integrated Circuits Conference, CICC 2020
CountryUnited States
CityBoston
Period3/22/203/25/20

Keywords

  • ASIC
  • conditional computing
  • Deep convolutional neural networks (DCNNs)
  • deep learning
  • energy-efficient accelerator

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • Cite this

    Kim, M., & Seo, J. S. (2020). Deep Convolutional Neural Network Accelerator Featuring Conditional Computing and Low External Memory Access. In 2020 IEEE Custom Integrated Circuits Conference, CICC 2020 [9075931] (Proceedings of the Custom Integrated Circuits Conference; Vol. 2020-March). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CICC48029.2020.9075931