DC-line current ripple reduction of a parallel hybrid modular multilevel HVDC converter

Jiangchao Qin, Maryam Saeedifard

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Parallel hybrid modular multilevel converter (PH-MMC) is one of the potential converter topologies for highvoltage direct-current (HVDC) transmission systems. Due to the circuit topology of a PHMMC, the dc-bus voltage contains low-order harmonics and cannot be fully regulated at a constant dc voltage. This paper proposes a zero-sequence voltage injection (ZSVI)-based model predictive control (MPC) strategy to control the dc current/power flow and simultaneously minimize the dc-current ripple. The proposed strategy takes the advantage of a cost function minimization technique to determine and inject the optimal zero-sequence voltage components into the dc-bus voltage of a PHMMC system. Performance of the proposed strategy for a 21-level PHMMC-based HVDC station system is evaluated in the PSCAD/EMTDC software environment. The reported results demonstrate the proposed ZSVI-MPC strategy can regulate the dc current while reducing its ripple.

Original languageEnglish (US)
Title of host publicationIEEE Power and Energy Society General Meeting
PublisherIEEE Computer Society
Volume2014-October
EditionOctober
DOIs
StatePublished - Oct 29 2014
Externally publishedYes
Event2014 IEEE Power and Energy Society General Meeting - National Harbor, United States
Duration: Jul 27 2014Jul 31 2014

Other

Other2014 IEEE Power and Energy Society General Meeting
CountryUnited States
CityNational Harbor
Period7/27/147/31/14

Fingerprint

Electric potential
Model predictive control
Electric network topology
Cost functions
Topology

ASJC Scopus subject areas

  • Energy Engineering and Power Technology
  • Nuclear Energy and Engineering
  • Renewable Energy, Sustainability and the Environment
  • Electrical and Electronic Engineering

Cite this

Qin, J., & Saeedifard, M. (2014). DC-line current ripple reduction of a parallel hybrid modular multilevel HVDC converter. In IEEE Power and Energy Society General Meeting (October ed., Vol. 2014-October). [6939346] IEEE Computer Society. https://doi.org/10.1109/PESGM.2014.6939346

DC-line current ripple reduction of a parallel hybrid modular multilevel HVDC converter. / Qin, Jiangchao; Saeedifard, Maryam.

IEEE Power and Energy Society General Meeting. Vol. 2014-October October. ed. IEEE Computer Society, 2014. 6939346.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Qin, J & Saeedifard, M 2014, DC-line current ripple reduction of a parallel hybrid modular multilevel HVDC converter. in IEEE Power and Energy Society General Meeting. October edn, vol. 2014-October, 6939346, IEEE Computer Society, 2014 IEEE Power and Energy Society General Meeting, National Harbor, United States, 7/27/14. https://doi.org/10.1109/PESGM.2014.6939346
Qin J, Saeedifard M. DC-line current ripple reduction of a parallel hybrid modular multilevel HVDC converter. In IEEE Power and Energy Society General Meeting. October ed. Vol. 2014-October. IEEE Computer Society. 2014. 6939346 https://doi.org/10.1109/PESGM.2014.6939346
Qin, Jiangchao ; Saeedifard, Maryam. / DC-line current ripple reduction of a parallel hybrid modular multilevel HVDC converter. IEEE Power and Energy Society General Meeting. Vol. 2014-October October. ed. IEEE Computer Society, 2014.
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