TY - GEN
T1 - Data storage time sensitive ECC schemes for MLC NAND Flash memories
AU - Yang, C.
AU - Muckatira, D.
AU - Kulkarni, A.
AU - Chakrabarti, Chaitali
N1 - Copyright:
Copyright 2014 Elsevier B.V., All rights reserved.
PY - 2013/10/18
Y1 - 2013/10/18
N2 - Errors in MLC NAND Flash can be classified into retention errors and program interference (PI) errors. While retention errors are dominant when the data storage time is greater than 1 day, PI errors are dominant for short data storage times. Furthermore these two types of errors have different probabilities of 0->1 or 1->0 bit flips. We utilize the characteristics of the two types of errors in the development of ECC schemes for applications that have different storage times. In both cases, we first apply Gray coding and 2-bit interleaving. The corresponding most significant bit (MSB) and least significant bit (LSB) sub-page has only one type of dominating error (0->1 or 1->0). Next we form a product code using linear block code along rows and even parity check along columns to detect all the possible error locations. We develop an algorithm to choose errors among the possible error locations based on the dominant error type. Performance simulation and hardware implementation results show that the proposed solutions have the same performance as BCH codes with larger error correction capability but with significantly lower hardware overhead. For instance, for a 2KB MLC Flash used in long storage time applications, the proposed ECC scheme has 50% lower energy and 60% lower decoding latency compared to the BCH scheme.
AB - Errors in MLC NAND Flash can be classified into retention errors and program interference (PI) errors. While retention errors are dominant when the data storage time is greater than 1 day, PI errors are dominant for short data storage times. Furthermore these two types of errors have different probabilities of 0->1 or 1->0 bit flips. We utilize the characteristics of the two types of errors in the development of ECC schemes for applications that have different storage times. In both cases, we first apply Gray coding and 2-bit interleaving. The corresponding most significant bit (MSB) and least significant bit (LSB) sub-page has only one type of dominating error (0->1 or 1->0). Next we form a product code using linear block code along rows and even parity check along columns to detect all the possible error locations. We develop an algorithm to choose errors among the possible error locations based on the dominant error type. Performance simulation and hardware implementation results show that the proposed solutions have the same performance as BCH codes with larger error correction capability but with significantly lower hardware overhead. For instance, for a 2KB MLC Flash used in long storage time applications, the proposed ECC scheme has 50% lower energy and 60% lower decoding latency compared to the BCH scheme.
KW - Flash memories
KW - error correction codes
KW - multi-level cell
KW - retention and program interference errors
UR - http://www.scopus.com/inward/record.url?scp=84890460632&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84890460632&partnerID=8YFLogxK
U2 - 10.1109/ICASSP.2013.6638108
DO - 10.1109/ICASSP.2013.6638108
M3 - Conference contribution
AN - SCOPUS:84890460632
SN - 9781479903566
T3 - ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
SP - 2513
EP - 2517
BT - 2013 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2013 - Proceedings
T2 - 2013 38th IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2013
Y2 - 26 May 2013 through 31 May 2013
ER -