Current source based standard cell model for accurate signal integrity and timing analysis

Amit Goel, Sarma Vrudhula

Research output: Chapter in Book/Report/Conference proceedingConference contribution

16 Scopus citations

Abstract

The inductance and coupling effects in interconnects and non-linear receiver loads has resulted in complex input signals and output loads for gates in the modern deep sub-micron CMOS technologies. As a result, the conventional method of timing characterization, which is based on lookup tables with input slew and output load capacitance as indices, is no longer adequate. The focus has now shifted to current source based standard cell models which are based on the fundamental property of transconductance of MOSFETs. In this paper we propose a systematic methodology for obtaining a current based delay model for gates, which can accommodate both single (SIS) and multi-input (MIS) switching signals of arbitrary shape and complex non-linear output loads. We use an analytical model for the gate output current expressed as a function of the node voltages. This results in an average error less than 0.5% with maximum standard deviation of 2.5% in error when compared with SPICE for a large number of standard cells. When compared with SPICE, using the proposed models gives stage delay and output slew with an average error of less than 3% and 2% respectively for arbitrary inputs and output load combinations.

Original languageEnglish (US)
Title of host publicationDesign, Automation and Test in Europe, DATE 2008
Pages574-579
Number of pages6
DOIs
StatePublished - Aug 25 2008
EventDesign, Automation and Test in Europe, DATE 2008 - Munich, Germany
Duration: Mar 10 2008Mar 14 2008

Publication series

NameProceedings -Design, Automation and Test in Europe, DATE
ISSN (Print)1530-1591

Other

OtherDesign, Automation and Test in Europe, DATE 2008
CountryGermany
CityMunich
Period3/10/083/14/08

ASJC Scopus subject areas

  • Engineering(all)

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