11 Citations (Scopus)

Abstract

In this survey, the design challenges of cross-point memory arrays with emerging nonvolatile memory technologies are discussed. In particular, the write/read scheme for cross-point memory and the associated problems such as voltage drop along interconnect and sneak path current via unselected cells are analyzed. The write voltage margin and power consumption, as well as the read-current sensing margin and latency, are simulated with a voltage-mode sense amplifier for different array sizes and nonlinearity of the selector devices. Finally, state-of-the-art performance and mechanism of selector devices are summarized and they are classified as Type I selector with exponential current–voltage (I–V) characteristics and Type II selector with threshold I–V characteristics. Design challenges and device engineering guidelines are discussed for both types of selector in the summary.

Original languageEnglish (US)
Pages (from-to)1-8
Number of pages8
JournalJournal of Computational Electronics
DOIs
StateAccepted/In press - Aug 31 2017

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selectors
Selector
Data storage equipment
Voltage
Margin
Electric potential
margins
electric potential
Electric power utilization
Interconnect
Power Consumption
Latency
emerging
Sensing
amplifiers
nonlinearity
Design
engineering
Nonlinearity
Engineering

Keywords

  • Cross-point memory
  • Emerging NVM
  • Selector
  • Sneak path
  • Write/read margin

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Atomic and Molecular Physics, and Optics
  • Modeling and Simulation
  • Electrical and Electronic Engineering

Cite this

Cross-point memory design challenges and survey of selector device characteristics. / Peng, Xiaochen; Madler, Ryan; Chen, Pai Yu; Yu, Shimeng.

In: Journal of Computational Electronics, 31.08.2017, p. 1-8.

Research output: Contribution to journalArticle

Peng, Xiaochen ; Madler, Ryan ; Chen, Pai Yu ; Yu, Shimeng. / Cross-point memory design challenges and survey of selector device characteristics. In: Journal of Computational Electronics. 2017 ; pp. 1-8.
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