Abstract
A low-power content addressable memory (CAM)-tagged microprocessor cache using dynamic hierarchical NAND match lines is presented, emphasising the timing impact on overall cache design. Low-capacitive clock loading and lower NAND CAM match line activity factor provide a total cache tag power dissipation savings of up to 64 over a conventional design with NOR match lines. The circuit design, operation and physical layout are described. Results measured on a 0.13-m low standby power foundry process demonstrate 3.29fJ/bit/search CAM tag energy at VDD=0.9V and nearly 1GHz operating frequency at VDD=1.75V. The NAND match lines allow a completely critical race-free cache memory design, which improves robustness at high-scaled process technology nodes, while maintaining fast single-cycle access times.
Original language | English (US) |
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Pages (from-to) | 40-44 |
Number of pages | 5 |
Journal | IET Computers and Digital Techniques |
Volume | 2 |
Issue number | 1 |
DOIs | |
State | Published - 2008 |
ASJC Scopus subject areas
- Software
- Hardware and Architecture
- Electrical and Electronic Engineering