Critical race-free low-power NAND match line content addressable memory tagged cache memory

V. Chaudhary, T. H. Chen, F. Sheerin, L. T. Clark

Research output: Contribution to journalArticle

5 Citations (Scopus)

Abstract

A low-power content addressable memory (CAM)-tagged microprocessor cache using dynamic hierarchical NAND match lines is presented, emphasising the timing impact on overall cache design. Low-capacitive clock loading and lower NAND CAM match line activity factor provide a total cache tag power dissipation savings of up to 64 over a conventional design with NOR match lines. The circuit design, operation and physical layout are described. Results measured on a 0.13-m low standby power foundry process demonstrate 3.29fJ/bit/search CAM tag energy at VDD=0.9V and nearly 1GHz operating frequency at VDD=1.75V. The NAND match lines allow a completely critical race-free cache memory design, which improves robustness at high-scaled process technology nodes, while maintaining fast single-cycle access times.

Original languageEnglish (US)
Pages (from-to)40-44
Number of pages5
JournalIET Computers and Digital Techniques
Volume2
Issue number1
DOIs
StatePublished - 2008

Fingerprint

Associative storage
Cache memory
Foundries
Microprocessor chips
Clocks
Energy dissipation
Networks (circuits)

ASJC Scopus subject areas

  • Hardware and Architecture
  • Software
  • Electrical and Electronic Engineering

Cite this

Critical race-free low-power NAND match line content addressable memory tagged cache memory. / Chaudhary, V.; Chen, T. H.; Sheerin, F.; Clark, L. T.

In: IET Computers and Digital Techniques, Vol. 2, No. 1, 2008, p. 40-44.

Research output: Contribution to journalArticle

Chaudhary, V. ; Chen, T. H. ; Sheerin, F. ; Clark, L. T. / Critical race-free low-power NAND match line content addressable memory tagged cache memory. In: IET Computers and Digital Techniques. 2008 ; Vol. 2, No. 1. pp. 40-44.
@article{25fa9ad65aeb45efa8693d15a146e12c,
title = "Critical race-free low-power NAND match line content addressable memory tagged cache memory",
abstract = "A low-power content addressable memory (CAM)-tagged microprocessor cache using dynamic hierarchical NAND match lines is presented, emphasising the timing impact on overall cache design. Low-capacitive clock loading and lower NAND CAM match line activity factor provide a total cache tag power dissipation savings of up to 64 over a conventional design with NOR match lines. The circuit design, operation and physical layout are described. Results measured on a 0.13-m low standby power foundry process demonstrate 3.29fJ/bit/search CAM tag energy at VDD=0.9V and nearly 1GHz operating frequency at VDD=1.75V. The NAND match lines allow a completely critical race-free cache memory design, which improves robustness at high-scaled process technology nodes, while maintaining fast single-cycle access times.",
author = "V. Chaudhary and Chen, {T. H.} and F. Sheerin and Clark, {L. T.}",
year = "2008",
doi = "10.1049/iet-cdt:20070040",
language = "English (US)",
volume = "2",
pages = "40--44",
journal = "IET Computers and Digital Techniques",
issn = "1751-8601",
publisher = "Institution of Engineering and Technology",
number = "1",

}

TY - JOUR

T1 - Critical race-free low-power NAND match line content addressable memory tagged cache memory

AU - Chaudhary, V.

AU - Chen, T. H.

AU - Sheerin, F.

AU - Clark, L. T.

PY - 2008

Y1 - 2008

N2 - A low-power content addressable memory (CAM)-tagged microprocessor cache using dynamic hierarchical NAND match lines is presented, emphasising the timing impact on overall cache design. Low-capacitive clock loading and lower NAND CAM match line activity factor provide a total cache tag power dissipation savings of up to 64 over a conventional design with NOR match lines. The circuit design, operation and physical layout are described. Results measured on a 0.13-m low standby power foundry process demonstrate 3.29fJ/bit/search CAM tag energy at VDD=0.9V and nearly 1GHz operating frequency at VDD=1.75V. The NAND match lines allow a completely critical race-free cache memory design, which improves robustness at high-scaled process technology nodes, while maintaining fast single-cycle access times.

AB - A low-power content addressable memory (CAM)-tagged microprocessor cache using dynamic hierarchical NAND match lines is presented, emphasising the timing impact on overall cache design. Low-capacitive clock loading and lower NAND CAM match line activity factor provide a total cache tag power dissipation savings of up to 64 over a conventional design with NOR match lines. The circuit design, operation and physical layout are described. Results measured on a 0.13-m low standby power foundry process demonstrate 3.29fJ/bit/search CAM tag energy at VDD=0.9V and nearly 1GHz operating frequency at VDD=1.75V. The NAND match lines allow a completely critical race-free cache memory design, which improves robustness at high-scaled process technology nodes, while maintaining fast single-cycle access times.

UR - http://www.scopus.com/inward/record.url?scp=38649134782&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=38649134782&partnerID=8YFLogxK

U2 - 10.1049/iet-cdt:20070040

DO - 10.1049/iet-cdt:20070040

M3 - Article

AN - SCOPUS:38649134782

VL - 2

SP - 40

EP - 44

JO - IET Computers and Digital Techniques

JF - IET Computers and Digital Techniques

SN - 1751-8601

IS - 1

ER -