CPU generated binary and ternary loads for power delivery assessment

William Lambert, Raja Ayyanar

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

CPU generated loads useful for analysis and characterization of microprocessor power delivery networks are described along with potential applications. The loads are generated by a functional microprocessor operating in PLL BYPASS mode.

Original languageEnglish (US)
Title of host publicationIEEE 16th Topical Meeting on Electrical Performance of Electronic Packaging, EPEP
Pages3-6
Number of pages4
DOIs
StatePublished - Dec 1 2007
EventIEEE 16th Topical Meeting on Electrical Performance of Electronic Packaging, EPEP - Atlanta, GA, United States
Duration: Oct 29 2007Oct 31 2007

Publication series

NameIEEE Topical Meeting on Electrical Performance of Electronic Packaging

Other

OtherIEEE 16th Topical Meeting on Electrical Performance of Electronic Packaging, EPEP
CountryUnited States
CityAtlanta, GA
Period10/29/0710/31/07

ASJC Scopus subject areas

  • Engineering(all)

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