Cost-Effective Design Solutions for Enhancing PRAM Reliability and Performance

Phase change RAM (PRAM) is an emerging memory technology that has fast read access time, low standby power, and high storage density. Multi-level Cell (MLC) PRAM has even higher storage density but suffers from low reliability and long write latency. This paper investigates a set of cost-effective design solutions for enabling MLC PRAM to be used as a mainstream memory technology. Earlier, we had proposed a multi-level scheme to improve reliability through circuit level and architecture level tuning - the corresponding scheme is referred to as baseline. In this paper, we show how tuning the programming current profile at the device level helps reduce the error rates even further and enables the use of an even lower cost error control coding (ECC) to achieve the same level of reliability. We use a PRAM + DRAM hybrid memory configuration to analyze the tradeoffs between programming energy, IPC, and memory lifetime. We show that for the SPEC2006 and DeCapo benchmarks, a hybrid memory designed with 1 GB PRAM and 8 MB DRAM can achieve either longer lifetime or lower energy (compared to the baseline scheme) by tuning the programming current profile. For instance, if a BCH (t = 2) ECC unit is used, we can increase RESET programming pulse width to enhance memory lifetime by a factor of 10; for a fixed memory lifetime constraint of 10⁶ PRAM WRITE cycles, we can tune the programming current profile to achieve 27 percent memory energy saving with no loss in IPC.