Abstract

Phase change RAM (PRAM) is an emerging memory technology that has fast read access time, low standby power, and high storage density. Multi-level Cell (MLC) PRAM has even higher storage density but suffers from low reliability and long write latency. This paper investigates a set of cost-effective design solutions for enabling MLC PRAM to be used as a mainstream memory technology. Earlier, we had proposed a multi-level scheme to improve reliability through circuit level and architecture level tuning - the corresponding scheme is referred to as baseline. In this paper, we show how tuning the programming current profile at the device level helps reduce the error rates even further and enables the use of an even lower cost error control coding (ECC) to achieve the same level of reliability. We use a PRAM + DRAM hybrid memory configuration to analyze the tradeoffs between programming energy, IPC, and memory lifetime. We show that for the SPEC2006 and DeCapo benchmarks, a hybrid memory designed with 1 GB PRAM and 8 MB DRAM can achieve either longer lifetime or lower energy (compared to the baseline scheme) by tuning the programming current profile. For instance, if a BCH (t = 2) ECC unit is used, we can increase RESET programming pulse width to enhance memory lifetime by a factor of 10; for a fixed memory lifetime constraint of 106 PRAM WRITE cycles, we can tune the programming current profile to achieve 27 percent memory energy saving with no loss in IPC.

Original languageEnglish (US)
Article number7422141
Pages (from-to)1-11
Number of pages11
JournalIEEE Transactions on Multi-Scale Computing Systems
Volume3
Issue number1
DOIs
StatePublished - Jan 1 2017

Fingerprint

Random access storage
Data storage equipment
Costs
Computer programming
Tuning
Dynamic random access storage
Energy conservation
Networks (circuits)

Keywords

  • IPC
  • memory lifetime
  • Phase change memory
  • programming current profile tuning

ASJC Scopus subject areas

  • Control and Systems Engineering
  • Information Systems
  • Hardware and Architecture

Cite this

Cost-Effective Design Solutions for Enhancing PRAM Reliability and Performance. / Yang, Chengen; Mao, Manqing; Cao, Yu; Chakrabarti, Chaitali.

In: IEEE Transactions on Multi-Scale Computing Systems, Vol. 3, No. 1, 7422141, 01.01.2017, p. 1-11.

Research output: Contribution to journalArticle

@article{4486d2e7896243199cee92a8412ebfdb,
title = "Cost-Effective Design Solutions for Enhancing PRAM Reliability and Performance",
abstract = "Phase change RAM (PRAM) is an emerging memory technology that has fast read access time, low standby power, and high storage density. Multi-level Cell (MLC) PRAM has even higher storage density but suffers from low reliability and long write latency. This paper investigates a set of cost-effective design solutions for enabling MLC PRAM to be used as a mainstream memory technology. Earlier, we had proposed a multi-level scheme to improve reliability through circuit level and architecture level tuning - the corresponding scheme is referred to as baseline. In this paper, we show how tuning the programming current profile at the device level helps reduce the error rates even further and enables the use of an even lower cost error control coding (ECC) to achieve the same level of reliability. We use a PRAM + DRAM hybrid memory configuration to analyze the tradeoffs between programming energy, IPC, and memory lifetime. We show that for the SPEC2006 and DeCapo benchmarks, a hybrid memory designed with 1 GB PRAM and 8 MB DRAM can achieve either longer lifetime or lower energy (compared to the baseline scheme) by tuning the programming current profile. For instance, if a BCH (t = 2) ECC unit is used, we can increase RESET programming pulse width to enhance memory lifetime by a factor of 10; for a fixed memory lifetime constraint of 106 PRAM WRITE cycles, we can tune the programming current profile to achieve 27 percent memory energy saving with no loss in IPC.",
keywords = "IPC, memory lifetime, Phase change memory, programming current profile tuning",
author = "Chengen Yang and Manqing Mao and Yu Cao and Chaitali Chakrabarti",
year = "2017",
month = "1",
day = "1",
doi = "10.1109/TMSCS.2016.2536026",
language = "English (US)",
volume = "3",
pages = "1--11",
journal = "IEEE Transactions on Multi-Scale Computing Systems",
issn = "2332-7766",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "1",

}

TY - JOUR

T1 - Cost-Effective Design Solutions for Enhancing PRAM Reliability and Performance

AU - Yang, Chengen

AU - Mao, Manqing

AU - Cao, Yu

AU - Chakrabarti, Chaitali

PY - 2017/1/1

Y1 - 2017/1/1

N2 - Phase change RAM (PRAM) is an emerging memory technology that has fast read access time, low standby power, and high storage density. Multi-level Cell (MLC) PRAM has even higher storage density but suffers from low reliability and long write latency. This paper investigates a set of cost-effective design solutions for enabling MLC PRAM to be used as a mainstream memory technology. Earlier, we had proposed a multi-level scheme to improve reliability through circuit level and architecture level tuning - the corresponding scheme is referred to as baseline. In this paper, we show how tuning the programming current profile at the device level helps reduce the error rates even further and enables the use of an even lower cost error control coding (ECC) to achieve the same level of reliability. We use a PRAM + DRAM hybrid memory configuration to analyze the tradeoffs between programming energy, IPC, and memory lifetime. We show that for the SPEC2006 and DeCapo benchmarks, a hybrid memory designed with 1 GB PRAM and 8 MB DRAM can achieve either longer lifetime or lower energy (compared to the baseline scheme) by tuning the programming current profile. For instance, if a BCH (t = 2) ECC unit is used, we can increase RESET programming pulse width to enhance memory lifetime by a factor of 10; for a fixed memory lifetime constraint of 106 PRAM WRITE cycles, we can tune the programming current profile to achieve 27 percent memory energy saving with no loss in IPC.

AB - Phase change RAM (PRAM) is an emerging memory technology that has fast read access time, low standby power, and high storage density. Multi-level Cell (MLC) PRAM has even higher storage density but suffers from low reliability and long write latency. This paper investigates a set of cost-effective design solutions for enabling MLC PRAM to be used as a mainstream memory technology. Earlier, we had proposed a multi-level scheme to improve reliability through circuit level and architecture level tuning - the corresponding scheme is referred to as baseline. In this paper, we show how tuning the programming current profile at the device level helps reduce the error rates even further and enables the use of an even lower cost error control coding (ECC) to achieve the same level of reliability. We use a PRAM + DRAM hybrid memory configuration to analyze the tradeoffs between programming energy, IPC, and memory lifetime. We show that for the SPEC2006 and DeCapo benchmarks, a hybrid memory designed with 1 GB PRAM and 8 MB DRAM can achieve either longer lifetime or lower energy (compared to the baseline scheme) by tuning the programming current profile. For instance, if a BCH (t = 2) ECC unit is used, we can increase RESET programming pulse width to enhance memory lifetime by a factor of 10; for a fixed memory lifetime constraint of 106 PRAM WRITE cycles, we can tune the programming current profile to achieve 27 percent memory energy saving with no loss in IPC.

KW - IPC

KW - memory lifetime

KW - Phase change memory

KW - programming current profile tuning

UR - http://www.scopus.com/inward/record.url?scp=85016312433&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85016312433&partnerID=8YFLogxK

U2 - 10.1109/TMSCS.2016.2536026

DO - 10.1109/TMSCS.2016.2536026

M3 - Article

VL - 3

SP - 1

EP - 11

JO - IEEE Transactions on Multi-Scale Computing Systems

JF - IEEE Transactions on Multi-Scale Computing Systems

SN - 2332-7766

IS - 1

M1 - 7422141

ER -