Cost-effective concurrent test hardware design for linear analog circuits

Sule Ozev, Alex Orailoglu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

Concurrent detection of failures in analog circuits is becoming increasingly more important as safety-critical systems become more widespread. A methodology for the automatic design of concurrent failure detection circuitry for linear analog systems is discussed in this paper. In contrast to previous approaches, the methodology aims at providing coverage in terms of all the circuit components while minimizing the loading overhead by reducing the number of internal circuit nodes that need to be tapped. Parameter tolerances are incorporated through either statistical or mathematical analysis to determine the threshold for failure alarm. Experimental results confirm that full coverage can be attained while keeping the hardware overhead within a pre-specified budget.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
Pages258-264
Number of pages7
StatePublished - 2002
Externally publishedYes
EventInternational Conference on Computer Design (ICCD'02) VLSI in Copmuters and Processors - Freiburg, Germany
Duration: Sep 16 2002Sep 18 2002

Other

OtherInternational Conference on Computer Design (ICCD'02) VLSI in Copmuters and Processors
CountryGermany
CityFreiburg
Period9/16/029/18/02

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ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Ozev, S., & Orailoglu, A. (2002). Cost-effective concurrent test hardware design for linear analog circuits. In Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors (pp. 258-264)