### Abstract

In this paper, an architecture suitable for real-time image coding using vector quantization is presented. This architecture is based on the concept of content-addressable memory (CAM) where the data is accessed simultaneously and in parallel on the basis of its content. In vector quantization(VQ), a set of representative vectors (codebook) is generated from a training set of vectors. The input vectors to be coded are quantized to the closest codeword of the codebook and the corresponding index(label) of the codeword is transmitted. Thus, VQ essentially involves a search operation to obtain the best match. Traditionally, the search mechanism is implemented sequentially, where each vector is compared with the codewords one at a time. For K input vectors of dimension L, and a codebook of size N, the search complexity is of order K*L*N which is heavily compute intensive making real-time implementation of VQ algorithm difficult. The architectures reported thus far employ parallelism in the directions of vector dimension L and codebook size N. However, as K≫N for image coding, a greater degree of paralleism can be obtained by employing parallelism in the directions of L and K. This means that matching must be performed from the perspective of the codewords; namely, for a given codeword, all input vectors are evaluated in parallel. A speedup of order K*L results if a content-addressable memory based implementation is employed. This speedup coupled with the gains in the execution time for the basic distortion operation, implies that codebook generation and encoding is possible in real-time (<15 milliseconds). The regular and iterable architecture is particularly well suited for VLSI implementation.

Original language | English (US) |
---|---|

Pages (from-to) | 169-181 |

Number of pages | 13 |

Journal | Proceedings of SPIE - The International Society for Optical Engineering |

Volume | 1099 |

DOIs | |

State | Published - Sep 5 1989 |

Externally published | Yes |

### Fingerprint

### ASJC Scopus subject areas

- Applied Mathematics
- Electronic, Optical and Magnetic Materials
- Condensed Matter Physics
- Electrical and Electronic Engineering
- Computer Science Applications

### Cite this

**Content-addressable memory architecture for image coding using vector quantization.** / Panchanathan, Sethuraman; Goldberg, M.

Research output: Contribution to journal › Article

*Proceedings of SPIE - The International Society for Optical Engineering*, vol. 1099, pp. 169-181. https://doi.org/10.1117/12.960466

}

TY - JOUR

T1 - Content-addressable memory architecture for image coding using vector quantization

AU - Panchanathan, Sethuraman

AU - Goldberg, M.

PY - 1989/9/5

Y1 - 1989/9/5

N2 - In this paper, an architecture suitable for real-time image coding using vector quantization is presented. This architecture is based on the concept of content-addressable memory (CAM) where the data is accessed simultaneously and in parallel on the basis of its content. In vector quantization(VQ), a set of representative vectors (codebook) is generated from a training set of vectors. The input vectors to be coded are quantized to the closest codeword of the codebook and the corresponding index(label) of the codeword is transmitted. Thus, VQ essentially involves a search operation to obtain the best match. Traditionally, the search mechanism is implemented sequentially, where each vector is compared with the codewords one at a time. For K input vectors of dimension L, and a codebook of size N, the search complexity is of order K*L*N which is heavily compute intensive making real-time implementation of VQ algorithm difficult. The architectures reported thus far employ parallelism in the directions of vector dimension L and codebook size N. However, as K≫N for image coding, a greater degree of paralleism can be obtained by employing parallelism in the directions of L and K. This means that matching must be performed from the perspective of the codewords; namely, for a given codeword, all input vectors are evaluated in parallel. A speedup of order K*L results if a content-addressable memory based implementation is employed. This speedup coupled with the gains in the execution time for the basic distortion operation, implies that codebook generation and encoding is possible in real-time (<15 milliseconds). The regular and iterable architecture is particularly well suited for VLSI implementation.

AB - In this paper, an architecture suitable for real-time image coding using vector quantization is presented. This architecture is based on the concept of content-addressable memory (CAM) where the data is accessed simultaneously and in parallel on the basis of its content. In vector quantization(VQ), a set of representative vectors (codebook) is generated from a training set of vectors. The input vectors to be coded are quantized to the closest codeword of the codebook and the corresponding index(label) of the codeword is transmitted. Thus, VQ essentially involves a search operation to obtain the best match. Traditionally, the search mechanism is implemented sequentially, where each vector is compared with the codewords one at a time. For K input vectors of dimension L, and a codebook of size N, the search complexity is of order K*L*N which is heavily compute intensive making real-time implementation of VQ algorithm difficult. The architectures reported thus far employ parallelism in the directions of vector dimension L and codebook size N. However, as K≫N for image coding, a greater degree of paralleism can be obtained by employing parallelism in the directions of L and K. This means that matching must be performed from the perspective of the codewords; namely, for a given codeword, all input vectors are evaluated in parallel. A speedup of order K*L results if a content-addressable memory based implementation is employed. This speedup coupled with the gains in the execution time for the basic distortion operation, implies that codebook generation and encoding is possible in real-time (<15 milliseconds). The regular and iterable architecture is particularly well suited for VLSI implementation.

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U2 - 10.1117/12.960466

DO - 10.1117/12.960466

M3 - Article

AN - SCOPUS:84918677394

VL - 1099

SP - 169

EP - 181

JO - Proceedings of SPIE - The International Society for Optical Engineering

JF - Proceedings of SPIE - The International Society for Optical Engineering

SN - 0277-786X

ER -