Content-addressable memory architecture for image coding using vector quantization

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3 Citations (Scopus)

Abstract

In this paper, an architecture suitable for real-time image coding using vector quantization is presented. This architecture is based on the concept of content-addressable memory (CAM) where the data is accessed simultaneously and in parallel on the basis of its content. In vector quantization(VQ), a set of representative vectors (codebook) is generated from a training set of vectors. The input vectors to be coded are quantized to the closest codeword of the codebook and the corresponding index(label) of the codeword is transmitted. Thus, VQ essentially involves a search operation to obtain the best match. Traditionally, the search mechanism is implemented sequentially, where each vector is compared with the codewords one at a time. For K input vectors of dimension L, and a codebook of size N, the search complexity is of order K*L*N which is heavily compute intensive making real-time implementation of VQ algorithm difficult. The architectures reported thus far employ parallelism in the directions of vector dimension L and codebook size N. However, as K≫N for image coding, a greater degree of paralleism can be obtained by employing parallelism in the directions of L and K. This means that matching must be performed from the perspective of the codewords; namely, for a given codeword, all input vectors are evaluated in parallel. A speedup of order K*L results if a content-addressable memory based implementation is employed. This speedup coupled with the gains in the execution time for the basic distortion operation, implies that codebook generation and encoding is possible in real-time (<15 milliseconds). The regular and iterable architecture is particularly well suited for VLSI implementation.

Original languageEnglish (US)
Pages (from-to)169-181
Number of pages13
JournalProceedings of SPIE - The International Society for Optical Engineering
Volume1099
DOIs
StatePublished - Sep 5 1989
Externally publishedYes

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Associative storage
associative memory
Memory architecture
vector quantization
Image Coding
Vector Quantization
Codebook
Vector quantization
Image coding
coding
Set of vectors
Real-time
Parallelism
Speedup
Execution Time
Encoding
very large scale integration
Architecture
Imply
Labels

ASJC Scopus subject areas

  • Applied Mathematics
  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Computer Science Applications

Cite this

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abstract = "In this paper, an architecture suitable for real-time image coding using vector quantization is presented. This architecture is based on the concept of content-addressable memory (CAM) where the data is accessed simultaneously and in parallel on the basis of its content. In vector quantization(VQ), a set of representative vectors (codebook) is generated from a training set of vectors. The input vectors to be coded are quantized to the closest codeword of the codebook and the corresponding index(label) of the codeword is transmitted. Thus, VQ essentially involves a search operation to obtain the best match. Traditionally, the search mechanism is implemented sequentially, where each vector is compared with the codewords one at a time. For K input vectors of dimension L, and a codebook of size N, the search complexity is of order K*L*N which is heavily compute intensive making real-time implementation of VQ algorithm difficult. The architectures reported thus far employ parallelism in the directions of vector dimension L and codebook size N. However, as K≫N for image coding, a greater degree of paralleism can be obtained by employing parallelism in the directions of L and K. This means that matching must be performed from the perspective of the codewords; namely, for a given codeword, all input vectors are evaluated in parallel. A speedup of order K*L results if a content-addressable memory based implementation is employed. This speedup coupled with the gains in the execution time for the basic distortion operation, implies that codebook generation and encoding is possible in real-time (<15 milliseconds). The regular and iterable architecture is particularly well suited for VLSI implementation.",
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